/*
 * This file was generated by optab.pl - do not edit.
 */

#include "common-x86.h"
#include "operands-x86.h"
#include "optab-x86.h"
#include "regs-x86.h"

static struct x86OpCode Instructions[] = {
  { I_AAA, 0, { 0, 0, 0 }, "\x37", 1, -1, { -1, -1, -1 } },
  { I_AAD, 0, { 0, 0, 0 }, "\xD5\x0A", 2, -1, { -1, -1, -1 } },
  { I_AAD, 1, { IMMEDIATE|BITS8, 0, 0 }, "\xD5", 1, -1, { -1, -1, -1 } },
  { I_AAM, 0, { 0, 0, 0 }, "\xD4\x0A", 2, -1, { -1, -1, -1 } },
  { I_AAM, 1, { IMMEDIATE|BITS8, 0, 0 }, "\xD4", 1, -1, { -1, -1, -1 } },
  { I_AAS, 0, { 0, 0, 0 }, "\x3F", 1, -1, { -1, -1, -1 } },
  { I_ADC, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x14", 1, -1, { R_AL, -1, -1 } },
  { I_ADC, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x15", 1, -1, { R_AX, -1, -1 } },
  { I_ADC, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x15", 1, -1, { R_EAX, -1, -1 } },
  { I_ADC, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 2, { -1, -1, -1 } },
  { I_ADC, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 2, { -1, -1, -1 } },
  { I_ADC, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 2, { -1, -1, -1 } },
  { I_ADC, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 2, { -1, -1, -1 } },
  { I_ADC, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 2, { -1, -1, -1 } },
  { I_ADC, 2, { REGMEM|BITS8, REG8, 0 }, "\x10", 1, REGRM, { -1, -1, -1 } },
  { I_ADC, 2, { REGMEM|BITS16, REG16, 0 }, "\x11", 1, REGRM, { -1, -1, -1 } },
  { I_ADC, 2, { REGMEM|BITS32, REG32, 0 }, "\x11", 1, REGRM, { -1, -1, -1 } },
  { I_ADC, 2, { REG8, REGMEM|BITS8, 0 }, "\x12", 1, REGRM, { -1, -1, -1 } },
  { I_ADC, 2, { REG16, REGMEM|BITS16, 0 }, "\x13", 1, REGRM, { -1, -1, -1 } },
  { I_ADC, 2, { REG32, REGMEM|BITS32, 0 }, "\x13", 1, REGRM, { -1, -1, -1 } },
  { I_ADD, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x04", 1, -1, { R_AL, -1, -1 } },
  { I_ADD, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x05", 1, -1, { R_AX, -1, -1 } },
  { I_ADD, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x05", 1, -1, { R_EAX, -1, -1 } },
  { I_ADD, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 0, { -1, -1, -1 } },
  { I_ADD, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 0, { -1, -1, -1 } },
  { I_ADD, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 0, { -1, -1, -1 } },
  { I_ADD, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 0, { -1, -1, -1 } },
  { I_ADD, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 0, { -1, -1, -1 } },
  { I_ADD, 2, { REGMEM|BITS8, REG8, 0 }, "\x00", 1, REGRM, { -1, -1, -1 } },
  { I_ADD, 2, { REGMEM|BITS16, REG16, 0 }, "\x01", 1, REGRM, { -1, -1, -1 } },
  { I_ADD, 2, { REGMEM|BITS32, REG32, 0 }, "\x01", 1, REGRM, { -1, -1, -1 } },
  { I_ADD, 2, { REG8, REGMEM|BITS8, 0 }, "\x02", 1, REGRM, { -1, -1, -1 } },
  { I_ADD, 2, { REG16, REGMEM|BITS16, 0 }, "\x03", 1, REGRM, { -1, -1, -1 } },
  { I_ADD, 2, { REG32, REGMEM|BITS32, 0 }, "\x03", 1, REGRM, { -1, -1, -1 } },
  { I_ADDPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x58", 2, REGRM, { -1, -1, -1 } },
  { I_AND, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x24", 1, -1, { R_AL, -1, -1 } },
  { I_AND, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x25", 1, -1, { R_AX, -1, -1 } },
  { I_AND, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x25", 1, -1, { R_EAX, -1, -1 } },
  { I_AND, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 4, { -1, -1, -1 } },
  { I_AND, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 4, { -1, -1, -1 } },
  { I_AND, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 4, { -1, -1, -1 } },
  { I_AND, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 4, { -1, -1, -1 } },
  { I_AND, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 4, { -1, -1, -1 } },
  { I_AND, 2, { REGMEM|BITS8, REG8, 0 }, "\x20", 1, REGRM, { -1, -1, -1 } },
  { I_AND, 2, { REGMEM|BITS16, REG16, 0 }, "\x21", 1, REGRM, { -1, -1, -1 } },
  { I_AND, 2, { REGMEM|BITS32, REG32, 0 }, "\x21", 1, REGRM, { -1, -1, -1 } },
  { I_AND, 2, { REG8, REGMEM|BITS8, 0 }, "\x22", 1, REGRM, { -1, -1, -1 } },
  { I_AND, 2, { REG16, REGMEM|BITS16, 0 }, "\x23", 1, REGRM, { -1, -1, -1 } },
  { I_AND, 2, { REG32, REGMEM|BITS32, 0 }, "\x23", 1, REGRM, { -1, -1, -1 } },
  { I_ARPL, 2, { REGMEM|BITS16, REG16, 0 }, "\x63", 1, REGRM, { -1, -1, -1 } },
  { I_BOUND, 2, { REG16, MEMORY|BITS16, 0 }, "\x62", 1, REGRM, { -1, -1, -1 } },
  { I_BOUND, 2, { REG32, MEMORY|BITS32, 0 }, "\x62", 1, REGRM, { -1, -1, -1 } },
  { I_BSF, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\xBC", 2, REGRM, { -1, -1, -1 } },
  { I_BSF, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\xBC", 2, REGRM, { -1, -1, -1 } },
  { I_BSR, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\xBD", 2, REGRM, { -1, -1, -1 } },
  { I_BSR, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\xBD", 2, REGRM, { -1, -1, -1 } },
  { I_BSWAP, 1, { REG32, 0, 0 }, "\x0F\xC8", 2, REGCODE, { -1, -1, -1 } },
  { I_BT, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xA3", 2, REGRM, { -1, -1, -1 } },
  { I_BT, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xA3", 2, REGRM, { -1, -1, -1 } },
  { I_BT, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 4, { -1, -1, -1 } },
  { I_BT, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 4, { -1, -1, -1 } },
  { I_BTC, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xBB", 2, REGRM, { -1, -1, -1 } },
  { I_BTC, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xBB", 2, REGRM, { -1, -1, -1 } },
  { I_BTC, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 7, { -1, -1, -1 } },
  { I_BTC, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 7, { -1, -1, -1 } },
  { I_BTR, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xB3", 2, REGRM, { -1, -1, -1 } },
  { I_BTR, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xB3", 2, REGRM, { -1, -1, -1 } },
  { I_BTR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 6, { -1, -1, -1 } },
  { I_BTR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 6, { -1, -1, -1 } },
  { I_BTS, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xAB", 2, REGRM, { -1, -1, -1 } },
  { I_BTS, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xAB", 2, REGRM, { -1, -1, -1 } },
  { I_BTS, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 5, { -1, -1, -1 } },
  { I_BTS, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 5, { -1, -1, -1 } },
  { I_CALL, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\xE8", 1, -1, { -1, -1, -1 } },
  { I_CALL, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\xE8", 1, -1, { -1, -1, -1 } },
  { I_CALL, 1, { REGMEM|BITS16|NEAR, 0, 0 }, "\xFF", 1, 2, { -1, -1, -1 } },
  { I_CALL, 1, { REGMEM|BITS32|NEAR, 0, 0 }, "\xFF", 1, 2, { -1, -1, -1 } },
  { I_CALL, 1, { SEG16|OFF16|FAR, 0, 0 }, "\x9A", 1, -1, { -1, -1, -1 } },
  { I_CALL, 1, { SEG16|OFF32|BITS32|FAR, 0, 0 }, "\x9A", 1, -1, { -1, -1, -1 } },
  { I_CALL, 1, { REGMEM|BITS16|FAR, 0, 0 }, "\xFF", 1, 3, { -1, -1, -1 } },
  { I_CALL, 1, { REGMEM|BITS32|FAR, 0, 0 }, "\xFF", 1, 3, { -1, -1, -1 } },
  { I_CBW, 0, { 0, 0, 0 }, "\x98", 1, -1, { -1, -1, -1 } },
  { I_CDQ, 0, { BITS32, 0, 0 }, "\x99", 1, -1, { -1, -1, -1 } },
  { I_CLC, 0, { 0, 0, 0 }, "\xF8", 1, -1, { -1, -1, -1 } },
  { I_CLD, 0, { 0, 0, 0 }, "\xFC", 1, -1, { -1, -1, -1 } },
  { I_CLI, 0, { 0, 0, 0 }, "\xFA", 1, -1, { -1, -1, -1 } },
  { I_CLTS, 0, { 0, 0, 0 }, "\x0F\x06", 2, -1, { -1, -1, -1 } },
  { I_CMC, 0, { 0, 0, 0 }, "\xF5", 1, -1, { -1, -1, -1 } },
  { I_CMOVA, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x47", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVA, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x47", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVC, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x42", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVC, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x42", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVE, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x44", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVE, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x44", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVG, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4F", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVG, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4F", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVL, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4C", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVL, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4C", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVLE, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4E", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVLE, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4E", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNA, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x46", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNA, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x46", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNC, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x43", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNC, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x43", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNE, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x45", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNE, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x45", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNL, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4D", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNL, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4D", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNO, 2, { REG16, REGMEM|BITS32, 0 }, "\x0F\x41", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNO, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x41", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNP, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4B", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNP, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4B", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNS, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x49", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVNS, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x49", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVO, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x40", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVO, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x40", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVP, 2, { REG16, REGMEM|BITS32, 0 }, "\x0F\x4A", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVP, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4A", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVS, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x48", 2, REGRM, { -1, -1, -1 } },
  { I_CMOVS, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x48", 2, REGRM, { -1, -1, -1 } },
  { I_CMP, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x3C", 1, -1, { R_AL, -1, -1 } },
  { I_CMP, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x3D", 1, -1, { R_AX, -1, -1 } },
  { I_CMP, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x3D", 1, -1, { R_EAX, -1, -1 } },
  { I_CMP, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 7, { -1, -1, -1 } },
  { I_CMP, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 7, { -1, -1, -1 } },
  { I_CMP, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 7, { -1, -1, -1 } },
  { I_CMP, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 7, { -1, -1, -1 } },
  { I_CMP, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 7, { -1, -1, -1 } },
  { I_CMP, 2, { REGMEM|BITS8, REG8, 0 }, "\x38", 1, REGRM, { -1, -1, -1 } },
  { I_CMP, 2, { REGMEM|BITS16, REG16, 0 }, "\x39", 1, REGRM, { -1, -1, -1 } },
  { I_CMP, 2, { REGMEM|BITS32, REG32, 0 }, "\x39", 1, REGRM, { -1, -1, -1 } },
  { I_CMP, 2, { REG8, REGMEM|BITS8, 0 }, "\x3A", 1, REGRM, { -1, -1, -1 } },
  { I_CMP, 2, { REG16, REGMEM|BITS16, 0 }, "\x3B", 1, REGRM, { -1, -1, -1 } },
  { I_CMP, 2, { REG32, REGMEM|BITS32, 0 }, "\x3B", 1, REGRM, { -1, -1, -1 } },
  { I_CMPSB, 0, { 0, 0, 0 }, "\xA6", 1, -1, { -1, -1, -1 } },
  { I_CMPSD, 0, { BITS32, 0, 0 }, "\xA7", 1, -1, { -1, -1, -1 } },
  { I_CMPSW, 0, { 0, 0, 0 }, "\xA7", 1, -1, { -1, -1, -1 } },
  { I_CMPXCHG, 2, { REGMEM|BITS8, REG8, 0 }, "\x0F\xB0", 2, REGRM, { -1, -1, -1 } },
  { I_CMPXCHG, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xB1", 2, REGRM, { -1, -1, -1 } },
  { I_CMPXCHG, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xB1", 2, REGRM, { -1, -1, -1 } },
  { I_CMPXCHG8B, 1, { MEMORY|BITS64, 0, 0 }, "\x0F\xC7", 2, 1, { -1, -1, -1 } },
  { I_CPUID, 0, { 0, 0, 0 }, "\x0F\xA2", 2, -1, { -1, -1, -1 } },
  { I_CWD, 0, { 0, 0, 0 }, "\x99", 1, -1, { -1, -1, -1 } },
  { I_CWDE, 0, { BITS32, 0, 0 }, "\x98", 1, -1, { -1, -1, -1 } },
  { I_DAA, 0, { 0, 0, 0 }, "\x27", 1, -1, { -1, -1, -1 } },
  { I_DAS, 0, { 0, 0, 0 }, "\x2F", 1, -1, { -1, -1, -1 } },
  { I_DEC, 1, { REGMEM|BITS8, 0, 0 }, "\xFE", 1, 1, { -1, -1, -1 } },
  { I_DEC, 1, { REGMEM|BITS16, 0, 0 }, "\xFF", 1, 1, { -1, -1, -1 } },
  { I_DEC, 1, { REGMEM|BITS32, 0, 0 }, "\xFF", 1, 1, { -1, -1, -1 } },
  { I_DEC, 1, { REG16, 0, 0 }, "\x48", 1, REGCODE, { -1, -1, -1 } },
  { I_DEC, 1, { REG32, 0, 0 }, "\x48", 1, REGCODE, { -1, -1, -1 } },
  { I_DIV, 1, { REGMEM|BITS8, 0, 0 }, "\xF6", 1, 6, { -1, -1, -1 } },
  { I_DIV, 1, { REGMEM|BITS16, 0, 0 }, "\xF7", 1, 6, { -1, -1, -1 } },
  { I_DIV, 1, { REGMEM|BITS32, 0, 0 }, "\xF7", 1, 6, { -1, -1, -1 } },
  { I_EMMS, 0, { 0, 0, 0 }, "\x0F\x77", 2, -1, { -1, -1, -1 } },
  { I_ENTER, 2, { IMMEDIATE|BITS16, IMMEDIATE|BITS8, 0 }, "\xC8", 1, -1, { -1, -1, -1 } },
  { I_F2XM1, 0, { 0, 0, 0 }, "\xD9\xF0", 2, -1, { -1, -1, -1 } },
  { I_FABS, 0, { 0, 0, 0 }, "\xD9\xE1", 2, -1, { -1, -1, -1 } },
  { I_FADD, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 0, { R_ST0, -1, -1 } },
  { I_FADD, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 0, { R_ST0, -1, -1 } },
  { I_FADD, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xC0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FADD, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xC0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FADDP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xC0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FBLD, 2, { REGISTER, MEMORY|BITS80, 0 }, "\xDF", 1, 4, { R_ST0, -1, -1 } },
  { I_FBSTP, 2, { MEMORY|BITS80, REGISTER, 0 }, "\xDF", 1, 6, { -1, R_ST0, -1 } },
  { I_FCHS, 1, { REGISTER, 0, 0 }, "\xD9\xE0", 2, -1, { R_ST0, -1, -1 } },
  { I_FCLEX, 0, { 0, 0, 0 }, "\x9B\xDB\xE2", 3, -1, { -1, -1, -1 } },
  { I_FCMOVB, 2, { REGISTER, REG_FPU, 0 }, "\xDA\xC0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCMOVBE, 2, { REGISTER, REG_FPU, 0 }, "\xDA\xD0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCMOVE, 2, { REGISTER, REG_FPU, 0 }, "\xDA\xC8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCMOVNB, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xC0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCMOVNBE, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xD0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCMOVNE, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xC8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCMOVNU, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xD8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCMOVU, 2, { REGISTER, REG_FPU, 0 }, "\xDA\xD8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCOM, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 2, { R_ST0, -1, -1 } },
  { I_FCOM, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 2, { R_ST0, -1, -1 } },
  { I_FCOM, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xD0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCOMI, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xF0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCOMIP, 2, { REGISTER, REG_FPU, 0 }, "\xDF\xF0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCOMP, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 3, { R_ST0, -1, -1 } },
  { I_FCOMP, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 3, { R_ST0, -1, -1 } },
  { I_FCOMP, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xD8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FCOMPP, 2, { REGISTER, REGISTER, 0 }, "\xDE\xD9", 2, -1, { R_ST1, R_ST0, -1 } },
  { I_FCOS, 1, { REGISTER, 0, 0 }, "\xD9\xFF", 2, -1, { R_ST0, -1, -1 } },
  { I_FDECSTP, 0, { 0, 0, 0 }, "\xD9\xF6", 2, -1, { -1, -1, -1 } },
  { I_FDIV, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 6, { R_ST0, -1, -1 } },
  { I_FDIV, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 6, { R_ST0, -1, -1 } },
  { I_FDIV, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xF0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FDIV, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xF8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FDIVP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xF8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FDIVR, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 7, { R_ST0, -1, -1 } },
  { I_FDIVR, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 7, { R_ST0, -1, -1 } },
  { I_FDIVR, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xF8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FDIVR, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xF0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FDIVRP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xF0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FFREE, 1, { REG_FPU, 0, 0 }, "\xDD\xC0", 2, FPUCODE, { -1, -1, -1 } },
  { I_FIADD, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 0, { R_ST0, -1, -1 } },
  { I_FIADD, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 0, { R_ST0, -1, -1 } },
  { I_FICOM, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 2, { R_ST0, -1, -1 } },
  { I_FICOM, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 2, { R_ST0, -1, -1 } },
  { I_FICOMP, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 3, { R_ST0, -1, -1 } },
  { I_FICOMP, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 3, { R_ST0, -1, -1 } },
  { I_FIDIV, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 6, { R_ST0, -1, -1 } },
  { I_FIDIV, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 6, { R_ST0, -1, -1 } },
  { I_FIDIVR, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 7, { R_ST0, -1, -1 } },
  { I_FIDIVR, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 7, { R_ST0, -1, -1 } },
  { I_FILD, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDF", 1, 0, { R_ST0, -1, -1 } },
  { I_FILD, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDB", 1, 0, { R_ST0, -1, -1 } },
  { I_FILD, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDF", 1, 5, { R_ST0, -1, -1 } },
  { I_FIMUL, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 1, { R_ST0, -1, -1 } },
  { I_FIMUL, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 1, { R_ST0, -1, -1 } },
  { I_FINCSTP, 0, { 0, 0, 0 }, "\xD9\xF7", 2, -1, { -1, -1, -1 } },
  { I_FINIT, 0, { 0, 0, 0 }, "\x9B\xDB\xE3", 3, -1, { -1, -1, -1 } },
  { I_FIST, 2, { MEMORY|BITS16, REGISTER, 0 }, "\xDF", 1, 2, { -1, R_ST0, -1 } },
  { I_FIST, 2, { MEMORY|BITS32, REGISTER, 0 }, "\xDB", 1, 2, { -1, R_ST0, -1 } },
  { I_FISTP, 2, { MEMORY|BITS16, REGISTER, 0 }, "\xDF", 1, 3, { -1, R_ST0, -1 } },
  { I_FISTP, 2, { MEMORY|BITS32, REGISTER, 0 }, "\xDB", 1, 3, { -1, R_ST0, -1 } },
  { I_FISTP, 2, { MEMORY|BITS64, REGISTER, 0 }, "\xDF", 1, 7, { -1, R_ST0, -1 } },
  { I_FISUB, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 4, { R_ST0, -1, -1 } },
  { I_FISUB, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 4, { R_ST0, -1, -1 } },
  { I_FISUBR, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 5, { R_ST0, -1, -1 } },
  { I_FISUBR, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 5, { R_ST0, -1, -1 } },
  { I_FLD, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD9", 1, 0, { R_ST0, -1, -1 } },
  { I_FLD, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDD", 1, 0, { R_ST0, -1, -1 } },
  { I_FLD, 2, { REGISTER, MEMORY|BITS80, 0 }, "\xDB", 1, 5, { R_ST0, -1, -1 } },
  { I_FLD, 1, { REG_FPU, 0, 0 }, "\xD9\xC0", 2, FPUCODE, { -1, -1, -1 } },
  { I_FLD1, 1, { REGISTER, 0, 0 }, "\xD9\xE8", 2, -1, { R_ST0, -1, -1 } },
  { I_FLDCW, 1, { REGMEM, 0, 0 }, "\xD9", 1, 5, { -1, -1, -1 } },
  { I_FLDENV, 1, { REGMEM, 0, 0 }, "\xD9", 1, 4, { -1, -1, -1 } },
  { I_FLDL2E, 1, { REGISTER, 0, 0 }, "\xD9\xEA", 2, -1, { R_ST0, -1, -1 } },
  { I_FLDL2T, 1, { REGISTER, 0, 0 }, "\xD9\xE9", 2, -1, { R_ST0, -1, -1 } },
  { I_FLDLG2, 1, { REGISTER, 0, 0 }, "\xD9\xEC", 2, -1, { R_ST0, -1, -1 } },
  { I_FLDLN2, 1, { REGISTER, 0, 0 }, "\xD9\xED", 2, -1, { R_ST0, -1, -1 } },
  { I_FLDPI, 1, { REGISTER, 0, 0 }, "\xD9\xEB", 2, -1, { R_ST0, -1, -1 } },
  { I_FLDZ, 1, { REGISTER, 0, 0 }, "\xD9\xEE", 2, -1, { R_ST0, -1, -1 } },
  { I_FMUL, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 1, { R_ST0, -1, -1 } },
  { I_FMUL, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 1, { R_ST0, -1, -1 } },
  { I_FMUL, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xC8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FMUL, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xC8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FMULP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xC8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FNCLEX, 0, { 0, 0, 0 }, "\xDB\xE2", 2, -1, { -1, -1, -1 } },
  { I_FNINIT, 0, { 0, 0, 0 }, "\xDB\xE3", 2, -1, { -1, -1, -1 } },
  { I_FNOP, 0, { 0, 0, 0 }, "\xD9\xD0", 2, -1, { -1, -1, -1 } },
  { I_FNSAVE, 2, { REGISTER, MEMORY, 0 }, "\xDD", 1, 6, { R_ST0, -1, -1 } },
  { I_FNSTCW, 1, { MEMORY, 0, 0 }, "\xD9", 1, 7, { -1, -1, -1 } },
  { I_FNSTENV, 1, { MEMORY, 0, 0 }, "\xD9", 1, 6, { -1, -1, -1 } },
  { I_FNSTSW, 1, { MEMORY|BITS16, 0, 0 }, "\xDD", 1, 7, { -1, -1, -1 } },
  { I_FNSTSW, 1, { REGISTER|BITS16, 0, 0 }, "\xDF\xE0", 2, -1, { R_AX, -1, -1 } },
  { I_FPATAN, 1, { REGISTER, 0, 0 }, "\xD9\xF3", 2, -1, { R_ST0, -1, -1 } },
  { I_FPREM, 1, { REGISTER, 0, 0 }, "\xD9\xF8", 2, -1, { R_ST0, -1, -1 } },
  { I_FPREM1, 1, { REGISTER, 0, 0 }, "\xD9\xF5", 2, -1, { R_ST0, -1, -1 } },
  { I_FPTAN, 1, { REGISTER, 0, 0 }, "\xD9\xF2", 2, -1, { R_ST0, -1, -1 } },
  { I_FRNDINT, 1, { REGISTER, 0, 0 }, "\xD9\xFC", 2, -1, { R_ST0, -1, -1 } },
  { I_FRSTOR, 2, { REGISTER, MEMORY, 0 }, "\xDD", 1, 4, { R_ST0, -1, -1 } },
  { I_FSAVE, 2, { REGISTER, MEMORY, 0 }, "\x9B\xDD", 2, 6, { R_ST0, -1, -1 } },
  { I_FSCALE, 1, { REGISTER, 0, 0 }, "\xD9\xFD", 2, -1, { R_ST0, -1, -1 } },
  { I_FSIN, 1, { REGISTER, 0, 0 }, "\xD9\xFE", 2, -1, { R_ST0, -1, -1 } },
  { I_FSINCOS, 1, { REGISTER, 0, 0 }, "\xD9\xFB", 2, -1, { R_ST0, -1, -1 } },
  { I_FSQRT, 1, { REGISTER, 0, 0 }, "\xD9\xFA", 2, -1, { R_ST0, -1, -1 } },
  { I_FST, 2, { MEMORY|BITS32, REGISTER, 0 }, "\xD9", 1, 2, { -1, R_ST0, -1 } },
  { I_FST, 2, { MEMORY|BITS64, REGISTER, 0 }, "\xDD", 1, 2, { -1, R_ST0, -1 } },
  { I_FST, 2, { REG_FPU, REGISTER, 0 }, "\xDD\xD0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FSTCW, 1, { MEMORY, 0, 0 }, "\x9B\xD9", 2, 7, { -1, -1, -1 } },
  { I_FSTENV, 1, { MEMORY, 0, 0 }, "\x9B\xD9", 2, 6, { -1, -1, -1 } },
  { I_FSTP, 2, { MEMORY|BITS32, REGISTER, 0 }, "\xD9", 1, 3, { -1, R_ST0, -1 } },
  { I_FSTP, 2, { MEMORY|BITS64, REGISTER, 0 }, "\xDD", 1, 3, { -1, R_ST0, -1 } },
  { I_FSTP, 2, { MEMORY|BITS80, REGISTER, 0 }, "\xDB", 1, 7, { -1, R_ST0, -1 } },
  { I_FSTP, 2, { REG_FPU, REGISTER, 0 }, "\xDD\xD8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FSTSW, 1, { MEMORY, 0, 0 }, "\x9B\xDD", 2, 7, { -1, -1, -1 } },
  { I_FSTSW, 1, { REGISTER|BITS16, 0, 0 }, "\x9B\xDF\xE0", 3, -1, { R_AX, -1, -1 } },
  { I_FSUB, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 4, { R_ST0, -1, -1 } },
  { I_FSUB, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 4, { R_ST0, -1, -1 } },
  { I_FSUB, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xE0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FSUB, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xE8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FSUBP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xE8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FSUBR, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 5, { R_ST0, -1, -1 } },
  { I_FSUBR, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 5, { R_ST0, -1, -1 } },
  { I_FSUBR, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xE8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FSUBR, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xE0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FSUBRP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xE0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { I_FTST, 1, { REGISTER, 0, 0 }, "\xD9\xE4", 2, -1, { R_ST0, -1, -1 } },
  { I_FUCOM, 1, { REG_FPU, 0, 0 }, "\xDD\xE0", 2, FPUCODE, { -1, -1, -1 } },
  { I_FUCOMI, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xE8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FUCOMIP, 2, { REGISTER, REG_FPU, 0 }, "\xDF\xE8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FUCOMP, 1, { REG_FPU, 0, 0 }, "\xDD\xE8", 2, FPUCODE, { -1, -1, -1 } },
  { I_FUCOMPP, 1, { REGISTER, 0, 0 }, "\xDA\xE9", 2, -1, { R_ST1, -1, -1 } },
  { I_FXAM, 1, { REGISTER, 0, 0 }, "\xD9\xE5", 2, -1, { R_ST0, -1, -1 } },
  { I_FXCH, 1, { REG_FPU, 0, 0 }, "\xD9\xC8", 2, FPUCODE, { -1, -1, -1 } },
  { I_FXTRACT, 1, { REGISTER, 0, 0 }, "\xD9\xF4", 2, -1, { R_ST0, -1, -1 } },
  { I_FYL2X, 1, { REGISTER, 0, 0 }, "\xD9\xF1", 2, -1, { R_ST0, -1, -1 } },
  { I_FYL2XP1, 1, { REGISTER, 0, 0 }, "\xD9\xF9", 2, -1, { R_ST0, -1, -1 } },
  { I_HLT, 0, { 0, 0, 0 }, "\xF4", 1, -1, { -1, -1, -1 } },
  { I_IDIV, 1, { REGMEM|BITS8, 0, 0 }, "\xF6", 1, 7, { -1, -1, -1 } },
  { I_IDIV, 1, { REGMEM|BITS16, 0, 0 }, "\xF7", 1, 7, { -1, -1, -1 } },
  { I_IDIV, 1, { REGMEM|BITS32, 0, 0 }, "\xF7", 1, 7, { -1, -1, -1 } },
  { I_IMUL, 1, { REGMEM|BITS8, 0, 0 }, "\xF6", 1, 5, { -1, -1, -1 } },
  { I_IMUL, 1, { REGMEM|BITS16, 0, 0 }, "\xF7", 1, 5, { -1, -1, -1 } },
  { I_IMUL, 1, { REGMEM|BITS32, 0, 0 }, "\xF7", 1, 5, { -1, -1, -1 } },
  { I_IMUL, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\xAF", 2, REGRM, { -1, -1, -1 } },
  { I_IMUL, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\xAF", 2, REGRM, { -1, -1, -1 } },
  { I_IMUL, 3, { REG16, REGMEM|BITS16, IMMEDIATE|BITS8 }, "\x6B", 1, REGRM, { -1, -1, -1 } },
  { I_IMUL, 3, { REG32, REGMEM|BITS32, IMMEDIATE|BITS8 }, "\x6B", 1, REGRM, { -1, -1, -1 } },
  { I_IMUL, 3, { REG16, REGMEM|BITS16, IMMEDIATE|BITS16 }, "\x69", 1, REGRM, { -1, -1, -1 } },
  { I_IMUL, 3, { REG32, REGMEM|BITS32, IMMEDIATE|BITS32 }, "\x69", 1, REGRM, { -1, -1, -1 } },
  { I_IN, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\xE4", 1, -1, { R_AL, -1, -1 } },
  { I_IN, 2, { REGISTER|BITS16, IMMEDIATE|BITS8, 0 }, "\xE5", 1, -1, { R_AX, -1, -1 } },
  { I_IN, 2, { REGISTER|BITS32, IMMEDIATE|BITS8, 0 }, "\xE5", 1, -1, { R_EAX, -1, -1 } },
  { I_IN, 2, { REGISTER|BITS8, REGISTER|BITS16, 0 }, "\xEC", 1, -1, { R_AL, R_DX, -1 } },
  { I_IN, 2, { REGISTER|BITS16, REGISTER|BITS16, 0 }, "\xED", 1, -1, { R_AX, R_DX, -1 } },
  { I_IN, 2, { REGISTER|BITS32, REGISTER|BITS16, 0 }, "\xED", 1, -1, { R_EAX, R_DX, -1 } },
  { I_INC, 1, { REGMEM|BITS8, 0, 0 }, "\xFE", 1, 0, { -1, -1, -1 } },
  { I_INC, 1, { REGMEM|BITS16, 0, 0 }, "\xFF", 1, 0, { -1, -1, -1 } },
  { I_INC, 1, { REGMEM|BITS32, 0, 0 }, "\xFF", 1, 0, { -1, -1, -1 } },
  { I_INC, 1, { REG16, 0, 0 }, "\x40", 1, REGCODE, { -1, -1, -1 } },
  { I_INC, 1, { REG32, 0, 0 }, "\x40", 1, REGCODE, { -1, -1, -1 } },
  { I_INSB, 0, { 0, 0, 0 }, "\x6C", 1, -1, { -1, -1, -1 } },
  { I_INSD, 0, { BITS32, 0, 0 }, "\x6D", 1, -1, { -1, -1, -1 } },
  { I_INSW, 0, { 0, 0, 0 }, "\x6D", 1, -1, { -1, -1, -1 } },
  { I_INT, 1, { IMMEDIATE|BITS8, 0, 0 }, "\xCD", 1, -1, { -1, -1, -1 } },
  { I_INT3, 0, { 0, 0, 0 }, "\xCC", 1, -1, { -1, -1, -1 } },
  { I_INTO, 0, { 0, 0, 0 }, "\xCE", 1, -1, { -1, -1, -1 } },
  { I_INVD, 0, { 0, 0, 0 }, "\x0F\x08", 2, -1, { -1, -1, -1 } },
  { I_INVLPG, 1, { MEMORY, 0, 0 }, "\x0F\x01", 2, 7, { -1, -1, -1 } },
  { I_IRET, 0, { 0, 0, 0 }, "\xCF", 1, -1, { -1, -1, -1 } },
  { I_IRETD, 0, { BITS32, 0, 0 }, "\xCF", 1, -1, { -1, -1, -1 } },
  { I_JA, 1, { RELATIVE|BITS8, 0, 0 }, "\x77", 1, -1, { -1, -1, -1 } },
  { I_JA, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x87", 2, -1, { -1, -1, -1 } },
  { I_JA, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x87", 2, -1, { -1, -1, -1 } },
  { I_JC, 1, { RELATIVE|BITS8, 0, 0 }, "\x72", 1, -1, { -1, -1, -1 } },
  { I_JC, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x82", 2, -1, { -1, -1, -1 } },
  { I_JC, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x82", 2, -1, { -1, -1, -1 } },
  { I_JCXZ, 1, { RELATIVE|BITS8, 0, 0 }, "\xE3", 1, -1, { -1, -1, -1 } },
  { I_JE, 1, { RELATIVE|BITS8, 0, 0 }, "\x74", 1, -1, { -1, -1, -1 } },
  { I_JE, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x84", 2, -1, { -1, -1, -1 } },
  { I_JE, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x84", 2, -1, { -1, -1, -1 } },
  { I_JG, 1, { RELATIVE|BITS8, 0, 0 }, "\x7F", 1, -1, { -1, -1, -1 } },
  { I_JG, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x8F", 2, -1, { -1, -1, -1 } },
  { I_JG, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x8F", 2, -1, { -1, -1, -1 } },
  { I_JL, 1, { RELATIVE|BITS8, 0, 0 }, "\x7C", 1, -1, { -1, -1, -1 } },
  { I_JL, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x8C", 2, -1, { -1, -1, -1 } },
  { I_JL, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x8C", 2, -1, { -1, -1, -1 } },
  { I_JLE, 1, { RELATIVE|BITS8, 0, 0 }, "\x7E", 1, -1, { -1, -1, -1 } },
  { I_JLE, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x8E", 2, -1, { -1, -1, -1 } },
  { I_JLE, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x8E", 2, -1, { -1, -1, -1 } },
  { I_JMP, 1, { RELATIVE|BITS8|SHORT, 0, 0 }, "\xEB", 1, -1, { -1, -1, -1 } },
  { I_JMP, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\xE9", 1, -1, { -1, -1, -1 } },
  { I_JMP, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\xE9", 1, -1, { -1, -1, -1 } },
  { I_JMP, 1, { REGMEM|BITS16|NEAR, 0, 0 }, "\xFF", 1, 4, { -1, -1, -1 } },
  { I_JMP, 1, { REGMEM|BITS32|NEAR, 0, 0 }, "\xFF", 1, 4, { -1, -1, -1 } },
  { I_JMP, 1, { SEG16|OFF16|FAR, 0, 0 }, "\xEA", 1, -1, { -1, -1, -1 } },
  { I_JMP, 1, { SEG16|OFF32|BITS32|FAR, 0, 0 }, "\xEA", 1, -1, { -1, -1, -1 } },
  { I_JMP, 1, { REGMEM|BITS16|FAR, 0, 0 }, "\xFF", 1, 5, { -1, -1, -1 } },
  { I_JMP, 1, { REGMEM|BITS32|FAR, 0, 0 }, "\xFF", 1, 5, { -1, -1, -1 } },
  { I_JNA, 1, { RELATIVE|BITS8, 0, 0 }, "\x76", 1, -1, { -1, -1, -1 } },
  { I_JNA, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x86", 2, -1, { -1, -1, -1 } },
  { I_JNA, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x86", 2, -1, { -1, -1, -1 } },
  { I_JNC, 1, { RELATIVE|BITS8, 0, 0 }, "\x73", 1, -1, { -1, -1, -1 } },
  { I_JNC, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x83", 2, -1, { -1, -1, -1 } },
  { I_JNC, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x83", 2, -1, { -1, -1, -1 } },
  { I_JNE, 1, { RELATIVE|BITS8, 0, 0 }, "\x75", 1, -1, { -1, -1, -1 } },
  { I_JNE, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x85", 2, -1, { -1, -1, -1 } },
  { I_JNE, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x85", 2, -1, { -1, -1, -1 } },
  { I_JNL, 1, { RELATIVE|BITS8, 0, 0 }, "\x7D", 1, -1, { -1, -1, -1 } },
  { I_JNL, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x8D", 2, -1, { -1, -1, -1 } },
  { I_JNL, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x8D", 2, -1, { -1, -1, -1 } },
  { I_JNO, 1, { RELATIVE|BITS8, 0, 0 }, "\x71", 1, -1, { -1, -1, -1 } },
  { I_JNO, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x81", 2, -1, { -1, -1, -1 } },
  { I_JNO, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x81", 2, -1, { -1, -1, -1 } },
  { I_JNP, 1, { RELATIVE|BITS8, 0, 0 }, "\x7B", 1, -1, { -1, -1, -1 } },
  { I_JNP, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x8B", 2, -1, { -1, -1, -1 } },
  { I_JNP, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x8B", 2, -1, { -1, -1, -1 } },
  { I_JNS, 1, { RELATIVE|BITS8, 0, 0 }, "\x79", 1, -1, { -1, -1, -1 } },
  { I_JNS, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x89", 2, -1, { -1, -1, -1 } },
  { I_JNS, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x89", 2, -1, { -1, -1, -1 } },
  { I_JO, 1, { RELATIVE|BITS8, 0, 0 }, "\x70", 1, -1, { -1, -1, -1 } },
  { I_JO, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x80", 2, -1, { -1, -1, -1 } },
  { I_JO, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x80", 2, -1, { -1, -1, -1 } },
  { I_JP, 1, { RELATIVE|BITS8, 0, 0 }, "\x7A", 1, -1, { -1, -1, -1 } },
  { I_JP, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x8A", 2, -1, { -1, -1, -1 } },
  { I_JP, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x8A", 2, -1, { -1, -1, -1 } },
  { I_JS, 1, { RELATIVE|BITS8, 0, 0 }, "\x78", 1, -1, { -1, -1, -1 } },
  { I_JS, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\x0F\x88", 2, -1, { -1, -1, -1 } },
  { I_JS, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\x0F\x88", 2, -1, { -1, -1, -1 } },
  { I_LAHF, 0, { 0, 0, 0 }, "\x9F", 1, -1, { -1, -1, -1 } },
  { I_LAR, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x02", 2, REGRM, { -1, -1, -1 } },
  { I_LAR, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x02", 2, REGRM, { -1, -1, -1 } },
  { I_LDS, 2, { REG16, REGMEM|BITS16, 0 }, "\xC5", 1, REGRM, { -1, -1, -1 } },
  { I_LDS, 2, { REG32, REGMEM|BITS32, 0 }, "\xC5", 1, REGRM, { -1, -1, -1 } },
  { I_LEA, 2, { REG16, MEMORY, 0 }, "\x8D", 1, REGRM, { -1, -1, -1 } },
  { I_LEA, 2, { REG32, MEMORY, 0 }, "\x8D", 1, REGRM, { -1, -1, -1 } },
  { I_LEAVE, 0, { 0, 0, 0 }, "\xC9", 1, -1, { -1, -1, -1 } },
  { I_LEAVE, 0, { BITS32, 0, 0 }, "\xC9", 1, -1, { -1, -1, -1 } },
  { I_LES, 2, { REG16, REGMEM|BITS16, 0 }, "\xC4", 1, REGRM, { -1, -1, -1 } },
  { I_LES, 2, { REG32, REGMEM|BITS32, 0 }, "\xC4", 1, REGRM, { -1, -1, -1 } },
  { I_LFS, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\xB4", 2, REGRM, { -1, -1, -1 } },
  { I_LFS, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\xB4", 2, REGRM, { -1, -1, -1 } },
  { I_LGDT, 1, { MEMORY|BITS16, 0, 0 }, "\x0F\x01", 2, 2, { -1, -1, -1 } },
  { I_LGS, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\xB5", 2, REGRM, { -1, -1, -1 } },
  { I_LGS, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\xB5", 2, REGRM, { -1, -1, -1 } },
  { I_LIDT, 1, { MEMORY|BITS32, 0, 0 }, "\x0F\x01", 2, 3, { -1, -1, -1 } },
  { I_LLDT, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 2, { -1, -1, -1 } },
  { I_LMSW, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x01", 2, 6, { -1, -1, -1 } },
  { I_LOCK, 0, { 0, 0, 0 }, "\xF0", 1, -1, { -1, -1, -1 } },
  { I_LODSB, 0, { 0, 0, 0 }, "\xAC", 1, -1, { -1, -1, -1 } },
  { I_LODSD, 0, { BITS32, 0, 0 }, "\xAD", 1, -1, { -1, -1, -1 } },
  { I_LODSW, 0, { 0, 0, 0 }, "\xAD", 1, -1, { -1, -1, -1 } },
  { I_LOOP, 1, { RELATIVE|BITS8, 0, 0 }, "\xE2", 1, -1, { -1, -1, -1 } },
  { I_LOOPE, 1, { RELATIVE|BITS8, 0, 0 }, "\xE1", 1, -1, { -1, -1, -1 } },
  { I_LOOPNE, 1, { RELATIVE|BITS8, 0, 0 }, "\xE0", 1, -1, { -1, -1, -1 } },
  { I_LSL, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x03", 2, REGRM, { -1, -1, -1 } },
  { I_LSL, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x03", 2, REGRM, { -1, -1, -1 } },
  { I_LSS, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\xB2", 2, REGRM, { -1, -1, -1 } },
  { I_LSS, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\xB2", 2, REGRM, { -1, -1, -1 } },
  { I_LTR, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 3, { -1, -1, -1 } },
  { I_MOV, 2, { REGMEM|BITS8, REG8, 0 }, "\x88", 1, REGRM, { -1, -1, -1 } },
  { I_MOV, 2, { REGMEM|BITS16, REG16, 0 }, "\x89", 1, REGRM, { -1, -1, -1 } },
  { I_MOV, 2, { REGMEM|BITS32, REG32, 0 }, "\x89", 1, REGRM, { -1, -1, -1 } },
  { I_MOV, 2, { REG8, REGMEM|BITS8, 0 }, "\x8A", 1, REGRM, { -1, -1, -1 } },
  { I_MOV, 2, { REG16, REGMEM|BITS16, 0 }, "\x8B", 1, REGRM, { -1, -1, -1 } },
  { I_MOV, 2, { REG32, REGMEM|BITS32, 0 }, "\x8B", 1, REGRM, { -1, -1, -1 } },
  { I_MOV, 2, { REGMEM|BITS16, REG_SR, 0 }, "\x8C", 1, REGRM, { -1, -1, -1 } },
  { I_MOV, 2, { REG_SR, REGMEM|BITS16, 0 }, "\x8E", 1, REGRM, { -1, -1, -1 } },
  { I_MOV, 2, { REGISTER|BITS8, MEMOFFS, 0 }, "\xA0", 1, -1, { R_AL, -1, -1 } },
  { I_MOV, 2, { REGISTER|BITS16, MEMOFFS, 0 }, "\xA1", 1, -1, { R_AX, -1, -1 } },
  { I_MOV, 2, { REGISTER|BITS32, MEMOFFS, 0 }, "\xA1", 1, -1, { R_EAX, -1, -1 } },
  { I_MOV, 2, { MEMOFFS, REGISTER|BITS8, 0 }, "\xA2", 1, -1, { -1, R_AL, -1 } },
  { I_MOV, 2, { MEMOFFS, REGISTER|BITS16, 0 }, "\xA3", 1, -1, { -1, R_AX, -1 } },
  { I_MOV, 2, { MEMOFFS, REGISTER|BITS32, 0 }, "\xA3", 1, -1, { -1, R_EAX, -1 } },
  { I_MOV, 2, { REG8, IMMEDIATE|BITS8, 0 }, "\xB0", 1, REGCODE, { -1, -1, -1 } },
  { I_MOV, 2, { REG16, IMMEDIATE|BITS16, 0 }, "\xB8", 1, REGCODE, { -1, -1, -1 } },
  { I_MOV, 2, { REG32, IMMEDIATE|BITS32, 0 }, "\xB8", 1, REGCODE, { -1, -1, -1 } },
  { I_MOV, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC6", 1, 0, { -1, -1, -1 } },
  { I_MOV, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\xC7", 1, 0, { -1, -1, -1 } },
  { I_MOV, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\xC7", 1, 0, { -1, -1, -1 } },
  { I_MOV, 2, { REG_CONTROL, REG32, 0 }, "\x0F\x22", 2, REGRM, { -1, MODFIELD_RM, -1 } },
  { I_MOV, 2, { REG32, REG_CONTROL, 0 }, "\x0F\x20", 2, REGRM, { MODFIELD_RM, -1, -1 } },
  { I_MOV, 2, { REG32, REG_DEBUG, 0 }, "\x0F\x21", 2, REGRM, { MODFIELD_RM, -1, -1 } },
  { I_MOV, 2, { REG_DEBUG, REG32, 0 }, "\x0F\x23", 2, REGRM, { -1, MODFIELD_RM, -1 } },
  { I_MOVAPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x28", 2, REGRM, { -1, -1, -1 } },
  { I_MOVAPS, 2, { MEMORY|BITS128, REG_XMM, 0 }, "\x0F\x29", 2, REGRM, { -1, -1, -1 } },
  { I_MOVD, 2, { REG_MMX, REGMEM|BITS32, 0 }, "\x0F\x6E", 2, REGRM, { -1, -1, -1 } },
  { I_MOVD, 2, { REGMEM|BITS32, REG_MMX, 0 }, "\x0F\x7E", 2, REGRM, { -1, -1, -1 } },
  { I_MOVHPS, 2, { REG_XMM, MEMORY|BITS64, 0 }, "\x0F\x16", 2, REGRM, { -1, -1, -1 } },
  { I_MOVHPS, 2, { MEMORY|BITS64, REG_XMM, 0 }, "\x0F\x17", 2, REGRM, { -1, -1, -1 } },
  { I_MOVLPS, 2, { REG_XMM, MEMORY|BITS64, 0 }, "\x0F\x12", 2, REGRM, { -1, -1, -1 } },
  { I_MOVLPS, 2, { MEMORY|BITS64, REG_XMM, 0 }, "\x0F\x13", 2, REGRM, { -1, -1, -1 } },
  { I_MOVMSKPS, 2, { REG32, REG_XMM, 0 }, "\x0F\x50", 2, REGRM, { -1, -1, -1 } },
  { I_MOVNTPS, 2, { MEMORY, REG_XMM, 0 }, "\x0F\x2B", 2, REGRM, { -1, -1, -1 } },
  { I_MOVNTQ, 2, { MEMORY, REG_MMX, 0 }, "\x0F\xE7", 2, REGRM, { -1, -1, -1 } },
  { I_MOVQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x6F", 2, REGRM, { -1, -1, -1 } },
  { I_MOVQ, 2, { MEMORY|BITS64, REG_MMX, 0 }, "\x0F\x7F", 2, REGRM, { -1, -1, -1 } },
  { I_MOVSB, 0, { 0, 0, 0 }, "\xA4", 1, -1, { -1, -1, -1 } },
  { I_MOVSD, 0, { BITS32, 0, 0 }, "\xA5", 1, -1, { -1, -1, -1 } },
  { I_MOVSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x10", 3, REGRM, { -1, -1, -1 } },
  { I_MOVSS, 2, { MEMORY|BITS128, REG_XMM, 0 }, "\xF3\x0F\x11", 3, REGRM, { -1, -1, -1 } },
  { I_MOVSW, 0, { 0, 0, 0 }, "\xA5", 1, -1, { -1, -1, -1 } },
  { I_MOVSX, 2, { REG16, REGMEM|BITS8, 0 }, "\x0F\xBE", 2, REGRM, { -1, -1, -1 } },
  { I_MOVSX, 2, { REG32, REGMEM|BITS8, 0 }, "\x0F\xBE", 2, REGRM, { -1, -1, -1 } },
  { I_MOVSX, 2, { REG32, REGMEM|BITS16, 0 }, "\x0F\xBF", 2, REGRM, { -1, -1, -1 } },
  { I_MOVUPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x10", 2, REGRM, { -1, -1, -1 } },
  { I_MOVUPS, 2, { MEMORY|BITS128, REG_XMM, 0 }, "\x0F\x11", 2, REGRM, { -1, -1, -1 } },
  { I_MOVZX, 2, { REG16, REGMEM|BITS8, 0 }, "\x0F\xB6", 2, REGRM, { -1, -1, -1 } },
  { I_MOVZX, 2, { REG32, REGMEM|BITS8, 0 }, "\x0F\xB6", 2, REGRM, { -1, -1, -1 } },
  { I_MOVZX, 2, { REG32, REGMEM|BITS16, 0 }, "\x0F\xB7", 2, REGRM, { -1, -1, -1 } },
  { I_MUL, 1, { REGMEM|BITS8, 0, 0 }, "\xF6", 1, 4, { -1, -1, -1 } },
  { I_MUL, 1, { REGMEM|BITS16, 0, 0 }, "\xF7", 1, 4, { -1, -1, -1 } },
  { I_MUL, 1, { REGMEM|BITS32, 0, 0 }, "\xF7", 1, 4, { -1, -1, -1 } },
  { I_MULPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x59", 2, REGRM, { -1, -1, -1 } },
  { I_MULSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x59", 3, REGRM, { -1, -1, -1 } },
  { I_NEG, 1, { REGMEM|BITS8, 0, 0 }, "\xF6", 1, 3, { -1, -1, -1 } },
  { I_NEG, 1, { REGMEM|BITS16, 0, 0 }, "\xF7", 1, 3, { -1, -1, -1 } },
  { I_NEG, 1, { REGMEM|BITS32, 0, 0 }, "\xF7", 1, 3, { -1, -1, -1 } },
  { I_NOP, 0, { 0, 0, 0 }, "\x90", 1, -1, { -1, -1, -1 } },
  { I_NOT, 1, { REGMEM|BITS8, 0, 0 }, "\xF6", 1, 2, { -1, -1, -1 } },
  { I_NOT, 1, { REGMEM|BITS16, 0, 0 }, "\xF7", 1, 2, { -1, -1, -1 } },
  { I_NOT, 1, { REGMEM|BITS32, 0, 0 }, "\xF7", 1, 2, { -1, -1, -1 } },
  { I_OR, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x0C", 1, -1, { R_AL, -1, -1 } },
  { I_OR, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x0D", 1, -1, { R_AX, -1, -1 } },
  { I_OR, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x0D", 1, -1, { R_EAX, -1, -1 } },
  { I_OR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 1, { -1, -1, -1 } },
  { I_OR, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 1, { -1, -1, -1 } },
  { I_OR, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 1, { -1, -1, -1 } },
  { I_OR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 1, { -1, -1, -1 } },
  { I_OR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 1, { -1, -1, -1 } },
  { I_OR, 2, { REGMEM|BITS8, REG8, 0 }, "\x08", 1, REGRM, { -1, -1, -1 } },
  { I_OR, 2, { REGMEM|BITS16, REG16, 0 }, "\x09", 1, REGRM, { -1, -1, -1 } },
  { I_OR, 2, { REGMEM|BITS32, REG32, 0 }, "\x09", 1, REGRM, { -1, -1, -1 } },
  { I_OR, 2, { REG8, REGMEM|BITS8, 0 }, "\x0A", 1, REGRM, { -1, -1, -1 } },
  { I_OR, 2, { REG16, REGMEM|BITS16, 0 }, "\x0B", 1, REGRM, { -1, -1, -1 } },
  { I_OR, 2, { REG32, REGMEM|BITS32, 0 }, "\x0B", 1, REGRM, { -1, -1, -1 } },
  { I_ORPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x56", 2, REGRM, { -1, -1, -1 } },
  { I_OUT, 2, { IMMEDIATE|BITS8, REGISTER|BITS8, 0 }, "\xE6", 1, -1, { -1, R_AL, -1 } },
  { I_OUT, 2, { IMMEDIATE|BITS8, REGISTER|BITS16, 0 }, "\xE7", 1, -1, { -1, R_AX, -1 } },
  { I_OUT, 2, { IMMEDIATE|BITS8, REGISTER|BITS32, 0 }, "\xE7", 1, -1, { -1, R_EAX, -1 } },
  { I_OUT, 2, { REGISTER|BITS16, REGISTER|BITS8, 0 }, "\xEE", 1, -1, { R_DX, R_AL, -1 } },
  { I_OUT, 2, { REGISTER|BITS16, REGISTER|BITS16, 0 }, "\xEF", 1, -1, { R_DX, R_AX, -1 } },
  { I_OUT, 2, { REGISTER|BITS16, REGISTER|BITS32, 0 }, "\xEF", 1, -1, { R_DX, R_EAX, -1 } },
  { I_OUTSB, 0, { 0, 0, 0 }, "\x6E", 1, -1, { -1, -1, -1 } },
  { I_OUTSD, 0, { BITS32, 0, 0 }, "\x6F", 1, -1, { -1, -1, -1 } },
  { I_OUTSW, 0, { 0, 0, 0 }, "\x6F", 1, -1, { -1, -1, -1 } },
  { I_PACKSSDW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x6B", 2, REGRM, { -1, -1, -1 } },
  { I_PACKSSWB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x63", 2, REGRM, { -1, -1, -1 } },
  { I_PACKUSWB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x67", 2, REGRM, { -1, -1, -1 } },
  { I_PADDB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xFC", 2, REGRM, { -1, -1, -1 } },
  { I_PADDD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xFE", 2, REGRM, { -1, -1, -1 } },
  { I_PADDSB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xEC", 2, REGRM, { -1, -1, -1 } },
  { I_PADDSW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xED", 2, REGRM, { -1, -1, -1 } },
  { I_PADDUSB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xDC", 2, REGRM, { -1, -1, -1 } },
  { I_PADDUSW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xDD", 2, REGRM, { -1, -1, -1 } },
  { I_PADDW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xFD", 2, REGRM, { -1, -1, -1 } },
  { I_PAND, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xDB", 2, REGRM, { -1, -1, -1 } },
  { I_PANDN, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xDF", 2, REGRM, { -1, -1, -1 } },
  { I_PAVGB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE0", 2, REGRM, { -1, -1, -1 } },
  { I_PAVGW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE3", 2, REGRM, { -1, -1, -1 } },
  { I_PCMPEQB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x74", 2, REGRM, { -1, -1, -1 } },
  { I_PCMPEQD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x76", 2, REGRM, { -1, -1, -1 } },
  { I_PCMPEQW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x75", 2, REGRM, { -1, -1, -1 } },
  { I_PCMPGTB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x64", 2, REGRM, { -1, -1, -1 } },
  { I_PCMPGTD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x66", 2, REGRM, { -1, -1, -1 } },
  { I_PCMPGTW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x65", 2, REGRM, { -1, -1, -1 } },
  { I_PEXTRW, 3, { REG32, REG_MMX, IMMEDIATE|BITS8 }, "\x0F\xC5", 2, REGRM, { -1, -1, -1 } },
  { I_PINSRW, 3, { REG_MMX, MEMORY|BITS16, IMMEDIATE|BITS8 }, "\x0F\xC4", 2, REGRM, { -1, -1, -1 } },
  { I_PMADDWD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF5", 2, REGRM, { -1, -1, -1 } },
  { I_PMAXSW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xEE", 2, REGRM, { -1, -1, -1 } },
  { I_PMAXUB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xDE", 2, REGRM, { -1, -1, -1 } },
  { I_PMINSW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xEA", 2, REGRM, { -1, -1, -1 } },
  { I_PMINUB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xDA", 2, REGRM, { -1, -1, -1 } },
  { I_PMOVMSKB, 2, { REG32, REG_MMX, 0 }, "\x0F\xD7", 2, REGRM, { -1, -1, -1 } },
  { I_PMULHUW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE4", 2, REGRM, { -1, -1, -1 } },
  { I_PMULHW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE5", 2, REGRM, { -1, -1, -1 } },
  { I_PMULLW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD5", 2, REGRM, { -1, -1, -1 } },
  { I_POP, 1, { MEMORY|BITS16, 0, 0 }, "\x8F", 1, 0, { -1, -1, -1 } },
  { I_POP, 1, { MEMORY|BITS32, 0, 0 }, "\x8F", 1, 0, { -1, -1, -1 } },
  { I_POP, 1, { REG16, 0, 0 }, "\x58", 1, REGCODE, { -1, -1, -1 } },
  { I_POP, 1, { REG32, 0, 0 }, "\x58", 1, REGCODE, { -1, -1, -1 } },
  { I_POP, 1, { REGISTER, 0, 0 }, "\x1F", 1, -1, { R_DS, -1, -1 } },
  { I_POP, 1, { REGISTER, 0, 0 }, "\x07", 1, -1, { R_ES, -1, -1 } },
  { I_POP, 1, { REGISTER, 0, 0 }, "\x17", 1, -1, { R_SS, -1, -1 } },
  { I_POP, 1, { REGISTER, 0, 0 }, "\x0F\xA1", 2, -1, { R_FS, -1, -1 } },
  { I_POP, 1, { REGISTER, 0, 0 }, "\x0F\xA9", 2, -1, { R_GS, -1, -1 } },
  { I_POPA, 0, { 0, 0, 0 }, "\x61", 1, -1, { -1, -1, -1 } },
  { I_POPAD, 0, { BITS32, 0, 0 }, "\x61", 1, -1, { -1, -1, -1 } },
  { I_POPF, 0, { 0, 0, 0 }, "\x9D", 1, -1, { -1, -1, -1 } },
  { I_POPFD, 0, { BITS32, 0, 0 }, "\x9D", 1, -1, { -1, -1, -1 } },
  { I_POR, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xEB", 2, REGRM, { -1, -1, -1 } },
  { I_PREFETCHNTA, 1, { MEMORY|BITS8, 0, 0 }, "\x0F\x18", 2, 0, { -1, -1, -1 } },
  { I_PREFETCHT0, 1, { MEMORY|BITS8, 0, 0 }, "\x0F\x18", 2, 1, { -1, -1, -1 } },
  { I_PREFETCHT1, 1, { MEMORY|BITS8, 0, 0 }, "\x0F\x18", 2, 2, { -1, -1, -1 } },
  { I_PREFETCHT2, 1, { MEMORY|BITS8, 0, 0 }, "\x0F\x18", 2, 3, { -1, -1, -1 } },
  { I_PSADBW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF6", 2, REGRM, { -1, -1, -1 } },
  { I_PSHUFW, 3, { REG_MMX, MEMORY|BITS64, IMMEDIATE|BITS8 }, "\x0F\x70", 2, REGRM, { -1, -1, -1 } },
  { I_PSLLD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF2", 2, REGRM, { -1, -1, -1 } },
  { I_PSLLD, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x72", 2, 6, { -1, -1, -1 } },
  { I_PSLLQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF3", 2, REGRM, { -1, -1, -1 } },
  { I_PSLLQ, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x73", 2, 6, { -1, -1, -1 } },
  { I_PSLLW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF1", 2, REGRM, { -1, -1, -1 } },
  { I_PSLLW, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x71", 2, 6, { -1, -1, -1 } },
  { I_PSRAD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE2", 2, REGRM, { -1, -1, -1 } },
  { I_PSRAD, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x72", 2, 4, { -1, -1, -1 } },
  { I_PSRAW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE1", 2, REGRM, { -1, -1, -1 } },
  { I_PSRAW, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x71", 2, 4, { -1, -1, -1 } },
  { I_PSRLD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD2", 2, REGRM, { -1, -1, -1 } },
  { I_PSRLD, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x72", 2, 2, { -1, -1, -1 } },
  { I_PSRLQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD3", 2, REGRM, { -1, -1, -1 } },
  { I_PSRLQ, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x73", 2, 2, { -1, -1, -1 } },
  { I_PSRLW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD1", 2, REGRM, { -1, -1, -1 } },
  { I_PSRLW, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x71", 2, 2, { -1, -1, -1 } },
  { I_PSUBB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF8", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xFA", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBSB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE8", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBSW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE9", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBUSB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD8", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBUSW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD9", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF9", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKHBW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x68", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKHDQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x6A", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKHWD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x69", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKLBW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x60", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKLDQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x62", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKLWD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x61", 2, REGRM, { -1, -1, -1 } },
  { I_PUSH, 1, { REGMEM|BITS16, 0, 0 }, "\xFF", 1, 6, { -1, -1, -1 } },
  { I_PUSH, 1, { REGMEM|BITS32, 0, 0 }, "\xFF", 1, 6, { -1, -1, -1 } },
  { I_PUSH, 1, { REG16, 0, 0 }, "\x50", 1, REGCODE, { -1, -1, -1 } },
  { I_PUSH, 1, { REG32, 0, 0 }, "\x50", 1, REGCODE, { -1, -1, -1 } },
  { I_PUSH, 1, { IMMEDIATE|BITS8, 0, 0 }, "\x6A", 1, -1, { -1, -1, -1 } },
  { I_PUSH, 1, { IMMEDIATE|BITS16, 0, 0 }, "\x68", 1, -1, { -1, -1, -1 } },
  { I_PUSH, 1, { IMMEDIATE|BITS32, 0, 0 }, "\x68", 1, -1, { -1, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x0E", 1, -1, { R_CS, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x16", 1, -1, { R_SS, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x1E", 1, -1, { R_DS, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x06", 1, -1, { R_ES, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x0F\xA0", 2, -1, { R_FS, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x0F\xA8", 2, -1, { R_GS, -1, -1 } },
  { I_PUSHA, 0, { 0, 0, 0 }, "\x60", 1, -1, { -1, -1, -1 } },
  { I_PUSHAD, 0, { BITS32, 0, 0 }, "\x60", 1, -1, { -1, -1, -1 } },
  { I_PUSHF, 0, { 0, 0, 0 }, "\x9C", 1, -1, { -1, -1, -1 } },
  { I_PUSHFD, 0, { BITS32, 0, 0 }, "\x9C", 1, -1, { -1, -1, -1 } },
  { I_PXOR, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xEF", 2, REGRM, { -1, -1, -1 } },
  { I_RCL, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 2, { -1, 1, -1 } },
  { I_RCL, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 2, { -1, R_CL, -1 } },
  { I_RCL, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 2, { -1, -1, -1 } },
  { I_RCL, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 2, { -1, 1, -1 } },
  { I_RCL, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 2, { -1, R_CL, -1 } },
  { I_RCL, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 2, { -1, -1, -1 } },
  { I_RCL, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 2, { -1, 1, -1 } },
  { I_RCL, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 2, { -1, R_CL, -1 } },
  { I_RCL, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 2, { -1, -1, -1 } },
  { I_RCPPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x53", 2, REGRM, { -1, -1, -1 } },
  { I_RCPSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x53", 3, REGRM, { -1, -1, -1 } },
  { I_RCR, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 3, { -1, 1, -1 } },
  { I_RCR, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 3, { -1, R_CL, -1 } },
  { I_RCR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 3, { -1, -1, -1 } },
  { I_RCR, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 3, { -1, 1, -1 } },
  { I_RCR, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 3, { -1, R_CL, -1 } },
  { I_RCR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 3, { -1, -1, -1 } },
  { I_RCR, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 3, { -1, 1, -1 } },
  { I_RCR, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 3, { -1, R_CL, -1 } },
  { I_RCR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 3, { -1, -1, -1 } },
  { I_RDMSR, 0, { 0, 0, 0 }, "\x0F\x32", 2, -1, { -1, -1, -1 } },
  { I_RDPMC, 0, { 0, 0, 0 }, "\x0F\x33", 2, -1, { -1, -1, -1 } },
  { I_RDTSC, 0, { 0, 0, 0 }, "\x0F\x31", 2, -1, { -1, -1, -1 } },
  { I_RETF, 0, { 0, 0, 0 }, "\xCB", 1, -1, { -1, -1, -1 } },
  { I_RETF, 1, { IMMEDIATE|BITS16, 0, 0 }, "\xCA", 1, -1, { -1, -1, -1 } },
  { I_RETN, 0, { 0, 0, 0 }, "\xC3", 1, -1, { -1, -1, -1 } },
  { I_RETN, 1, { IMMEDIATE|BITS16, 0, 0 }, "\xC2", 1, -1, { -1, -1, -1 } },
  { I_ROL, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 0, { -1, 1, -1 } },
  { I_ROL, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 0, { -1, R_CL, -1 } },
  { I_ROL, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 0, { -1, -1, -1 } },
  { I_ROL, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 0, { -1, 1, -1 } },
  { I_ROL, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 0, { -1, R_CL, -1 } },
  { I_ROL, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 0, { -1, -1, -1 } },
  { I_ROL, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 0, { -1, 1, -1 } },
  { I_ROL, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 0, { -1, R_CL, -1 } },
  { I_ROL, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 0, { -1, -1, -1 } },
  { I_ROR, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 1, { -1, 1, -1 } },
  { I_ROR, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 1, { -1, R_CL, -1 } },
  { I_ROR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 1, { -1, -1, -1 } },
  { I_ROR, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 1, { -1, 1, -1 } },
  { I_ROR, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 1, { -1, R_CL, -1 } },
  { I_ROR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 1, { -1, -1, -1 } },
  { I_ROR, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 1, { -1, 1, -1 } },
  { I_ROR, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 1, { -1, R_CL, -1 } },
  { I_ROR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 1, { -1, -1, -1 } },
  { I_RSM, 0, { 0, 0, 0 }, "\x0F\xAA", 2, -1, { -1, -1, -1 } },
  { I_RSQRTPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x52", 2, REGRM, { -1, -1, -1 } },
  { I_RSQRTSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x52", 3, REGRM, { -1, -1, -1 } },
  { I_SAHF, 0, { 0, 0, 0 }, "\x9E", 1, -1, { -1, -1, -1 } },
  { I_SAR, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 7, { -1, 1, -1 } },
  { I_SAR, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 7, { -1, R_CL, -1 } },
  { I_SAR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 7, { -1, -1, -1 } },
  { I_SAR, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 7, { -1, 1, -1 } },
  { I_SAR, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 7, { -1, R_CL, -1 } },
  { I_SAR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 7, { -1, -1, -1 } },
  { I_SAR, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 7, { -1, 1, -1 } },
  { I_SAR, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 7, { -1, R_CL, -1 } },
  { I_SAR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 7, { -1, -1, -1 } },
  { I_SBB, 2, { REGISTER, IMMEDIATE|BITS8, 0 }, "\x1C", 1, -1, { R_AL, -1, -1 } },
  { I_SBB, 2, { REGISTER, IMMEDIATE|BITS16, 0 }, "\x1D", 1, -1, { R_AX, -1, -1 } },
  { I_SBB, 2, { REGISTER, IMMEDIATE|BITS32, 0 }, "\x1D", 1, -1, { R_EAX, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS8, REG8, 0 }, "\x18", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS16, REG16, 0 }, "\x19", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS32, REG32, 0 }, "\x19", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REG8, REGMEM|BITS8, 0 }, "\x1A", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REG16, REGMEM|BITS16, 0 }, "\x1B", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REG32, REGMEM|BITS32, 0 }, "\x1B", 1, REGRM, { -1, -1, -1 } },
  { I_SCASB, 0, { 0, 0, 0 }, "\xAE", 1, -1, { -1, -1, -1 } },
  { I_SCASD, 0, { BITS32, 0, 0 }, "\xAF", 1, -1, { -1, -1, -1 } },
  { I_SCASW, 0, { 0, 0, 0 }, "\xAF", 1, -1, { -1, -1, -1 } },
  { I_SETA, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x97", 2, REGRM, { -1, -1, -1 } },
  { I_SETC, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x92", 2, REGRM, { -1, -1, -1 } },
  { I_SETE, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x94", 2, REGRM, { -1, -1, -1 } },
  { I_SETG, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9F", 2, REGRM, { -1, -1, -1 } },
  { I_SETL, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9C", 2, REGRM, { -1, -1, -1 } },
  { I_SETNA, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x96", 2, REGRM, { -1, -1, -1 } },
  { I_SETNC, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x93", 2, REGRM, { -1, -1, -1 } },
  { I_SETNE, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x95", 2, REGRM, { -1, -1, -1 } },
  { I_SETNG, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9E", 2, REGRM, { -1, -1, -1 } },
  { I_SETNL, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9D", 2, REGRM, { -1, -1, -1 } },
  { I_SETNO, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x91", 2, REGRM, { -1, -1, -1 } },
  { I_SETNP, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9B", 2, REGRM, { -1, -1, -1 } },
  { I_SETNS, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x99", 2, REGRM, { -1, -1, -1 } },
  { I_SETO, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x90", 2, REGRM, { -1, -1, -1 } },
  { I_SETP, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9A", 2, REGRM, { -1, -1, -1 } },
  { I_SETS, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x98", 2, REGRM, { -1, -1, -1 } },
  { I_SFENCE, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\xAE", 2, 7, { -1, -1, -1 } },
  { I_SGDT, 1, { MEMORY, 0, 0 }, "\x0F\x01", 2, 0, { -1, -1, -1 } },
  { I_SHL, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 4, { -1, 1, -1 } },
  { I_SHL, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 4, { -1, R_CL, -1 } },
  { I_SHL, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 4, { -1, -1, -1 } },
  { I_SHL, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 4, { -1, 1, -1 } },
  { I_SHL, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 4, { -1, R_CL, -1 } },
  { I_SHL, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 4, { -1, -1, -1 } },
  { I_SHL, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 4, { -1, 1, -1 } },
  { I_SHL, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 4, { -1, R_CL, -1 } },
  { I_SHL, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 4, { -1, -1, -1 } },
  { I_SHLD, 3, { REGMEM|BITS16, REG16, IMMEDIATE|BITS8 }, "\x0F\xA4", 2, REGRM, { -1, -1, -1 } },
  { I_SHLD, 3, { REGMEM|BITS16, REG16, REGISTER }, "\x0F\xA5", 2, REGRM, { -1, -1, R_CL } },
  { I_SHLD, 3, { REGMEM|BITS32, REG32, IMMEDIATE|BITS8 }, "\x0F\xA4", 2, REGRM, { -1, -1, -1 } },
  { I_SHLD, 3, { REGMEM|BITS32, REG32, REGISTER }, "\x0F\xA5", 2, REGRM, { -1, -1, R_CL } },
  { I_SHR, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 5, { -1, 1, -1 } },
  { I_SHR, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 5, { -1, R_CL, -1 } },
  { I_SHR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 5, { -1, -1, -1 } },
  { I_SHR, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 5, { -1, 1, -1 } },
  { I_SHR, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 5, { -1, R_CL, -1 } },
  { I_SHR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 5, { -1, -1, -1 } },
  { I_SHR, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 5, { -1, 1, -1 } },
  { I_SHR, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 5, { -1, R_CL, -1 } },
  { I_SHR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 5, { -1, -1, -1 } },
  { I_SHRD, 3, { REGMEM|BITS16, REG16, IMMEDIATE|BITS8 }, "\x0F\xAC", 2, REGRM, { -1, -1, -1 } },
  { I_SHRD, 3, { REGMEM|BITS16, REG16, REGISTER }, "\x0F\xAD", 2, REGRM, { -1, -1, R_CL } },
  { I_SHRD, 3, { REGMEM|BITS32, REG32, IMMEDIATE|BITS8 }, "\x0F\xAC", 2, REGRM, { -1, -1, -1 } },
  { I_SHRD, 3, { REGMEM|BITS32, REG32, REGISTER }, "\x0F\xAD", 2, REGRM, { -1, -1, R_CL } },
  { I_SHUFPS, 3, { REG_XMM, MEMORY|BITS128, IMMEDIATE|BITS8 }, "\x0F\xC6", 2, REGRM, { -1, -1, -1 } },
  { I_SIDT, 1, { MEMORY, 0, 0 }, "\x0F\x01", 2, 1, { -1, -1, -1 } },
  { I_SLDT, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 0, { -1, -1, -1 } },
  { I_SLDT, 1, { REGMEM|BITS32, 0, 0 }, "\x0F\x00", 2, 0, { -1, -1, -1 } },
  { I_SMSW, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x01", 2, 4, { -1, -1, -1 } },
  { I_SMSW, 1, { MEMORY|BITS32, 0, 0 }, "\x0F\x01", 2, 4, { -1, -1, -1 } },
  { I_SQRTPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x51", 2, REGRM, { -1, -1, -1 } },
  { I_SQRTSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x51", 3, REGRM, { -1, -1, -1 } },
  { I_STC, 0, { 0, 0, 0 }, "\xF9", 1, -1, { -1, -1, -1 } },
  { I_STD, 0, { 0, 0, 0 }, "\xFD", 1, -1, { -1, -1, -1 } },
  { I_STI, 0, { 0, 0, 0 }, "\xFB", 1, -1, { -1, -1, -1 } },
  { I_STMXCSR, 1, { MEMORY|BITS32, 0, 0 }, "\x0F\xAE", 2, 3, { -1, -1, -1 } },
  { I_STOSB, 0, { 0, 0, 0 }, "\xAA", 1, -1, { -1, -1, -1 } },
  { I_STOSD, 0, { BITS32, 0, 0 }, "\xAB", 1, -1, { -1, -1, -1 } },
  { I_STOSW, 0, { 0, 0, 0 }, "\xAB", 1, -1, { -1, -1, -1 } },
  { I_STR, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 1, { -1, -1, -1 } },
  { I_SUB, 2, { REGISTER, IMMEDIATE|BITS8, 0 }, "\x2C", 1, -1, { R_AL, -1, -1 } },
  { I_SUB, 2, { REGISTER, IMMEDIATE|BITS16, 0 }, "\x2D", 1, -1, { R_AX, -1, -1 } },
  { I_SUB, 2, { REGISTER, IMMEDIATE|BITS32, 0 }, "\x2D", 1, -1, { R_EAX, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS8, REG8, 0 }, "\x28", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS16, REG16, 0 }, "\x29", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS32, REG32, 0 }, "\x29", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REG8, REGMEM|BITS8, 0 }, "\x2A", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REG16, REGMEM|BITS16, 0 }, "\x2B", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REG32, REGMEM|BITS32, 0 }, "\x2B", 1, REGRM, { -1, -1, -1 } },
  { I_SUBPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x5C", 2, REGRM, { -1, -1, -1 } },
  { I_SUBSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x5C", 3, REGRM, { -1, -1, -1 } },
  { I_SYSENTER, 0, { 0, 0, 0 }, "\x0F\x34", 2, -1, { -1, -1, -1 } },
  { I_SYSEXIT, 0, { 0, 0, 0 }, "\x0F\x35", 2, -1, { -1, -1, -1 } },
  { I_TEST, 2, { REGISTER, IMMEDIATE|BITS8, 0 }, "\xA8", 1, -1, { R_AL, -1, -1 } },
  { I_TEST, 2, { REGISTER, IMMEDIATE|BITS16, 0 }, "\xA9", 1, -1, { R_AX, -1, -1 } },
  { I_TEST, 2, { REGISTER, IMMEDIATE|BITS32, 0 }, "\xA9", 1, -1, { R_EAX, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xF6", 1, 0, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\xF7", 1, 0, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\xF7", 1, 0, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS8, REG8, 0 }, "\x84", 1, REGRM, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS16, REG16, 0 }, "\x85", 1, REGRM, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS32, REG32, 0 }, "\x85", 1, REGRM, { -1, -1, -1 } },
  { I_UCOMISS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x2E", 2, REGRM, { -1, -1, -1 } },
  { I_UD2, 0, { 0, 0, 0 }, "\x0F\x0B", 2, -1, { -1, -1, -1 } },
  { I_UNPCKHPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x15", 2, REGRM, { -1, -1, -1 } },
  { I_UNPCKLPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x14", 2, REGRM, { -1, -1, -1 } },
  { I_VERR, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 4, { -1, -1, -1 } },
  { I_VERW, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 5, { -1, -1, -1 } },
  { I_WAIT, 0, { 0, 0, 0 }, "\x9B", 1, -1, { -1, -1, -1 } },
  { I_WBINVD, 0, { 0, 0, 0 }, "\x0F\x09", 2, -1, { -1, -1, -1 } },
  { I_WRMSR, 0, { 0, 0, 0 }, "\x0F\x30", 2, -1, { -1, -1, -1 } },
  { I_XADD, 2, { REGMEM|BITS8, REG8, 0 }, "\x0F\xC0", 2, REGRM, { -1, -1, -1 } },
  { I_XADD, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xC1", 2, REGRM, { -1, -1, -1 } },
  { I_XADD, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xC1", 2, REGRM, { -1, -1, -1 } },
  { I_XCHG, 2, { REGISTER, REG16, 0 }, "\x90", 1, REGCODE, { R_AX, -1, -1 } },
  { I_XCHG, 2, { REGISTER, REG32, 0 }, "\x90", 1, REGCODE, { R_EAX, -1, -1 } },
  { I_XCHG, 2, { REG8, REGMEM|BITS8, 0 }, "\x86", 1, REGRM, { -1, -1, -1 } },
  { I_XCHG, 2, { REG16, REGMEM|BITS16, 0 }, "\x87", 1, REGRM, { -1, -1, -1 } },
  { I_XCHG, 2, { REG32, REGMEM|BITS32, 0 }, "\x87", 1, REGRM, { -1, -1, -1 } },
  { I_XLATB, 0, { 0, 0, 0 }, "\xD7", 1, -1, { -1, -1, -1 } },
  { I_XOR, 2, { REGISTER, IMMEDIATE|BITS8, 0 }, "\x34", 1, -1, { R_AL, -1, -1 } },
  { I_XOR, 2, { REGISTER, IMMEDIATE|BITS16, 0 }, "\x35", 1, -1, { R_AX, -1, -1 } },
  { I_XOR, 2, { REGISTER, IMMEDIATE|BITS32, 0 }, "\x35", 1, -1, { R_EAX, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS8, REG8, 0 }, "\x30", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS16, REG16, 0 }, "\x31", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS32, REG32, 0 }, "\x31", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REG8, REGMEM|BITS8, 0 }, "\x32", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REG16, REGMEM|BITS16, 0 }, "\x33", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REG32, REGMEM|BITS32, 0 }, "\x33", 1, REGRM, { -1, -1, -1 } },
  { I_XORPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x57", 2, REGRM, { -1, -1, -1 } },
  { 0, 0, { 0, 0, 0 }, 0, 0, 0, { 0, 0, 0 } }
};

static struct x86OpCode *OpCode_00[] = {
  Instructions + 28,
  0
};

static struct x86OpCode *OpCode_01[] = {
  Instructions + 29,
  Instructions + 30,
  0
};

static struct x86OpCode *OpCode_02[] = {
  Instructions + 31,
  0
};

static struct x86OpCode *OpCode_03[] = {
  Instructions + 32,
  Instructions + 33,
  0
};

static struct x86OpCode *OpCode_04[] = {
  Instructions + 20,
  0
};

static struct x86OpCode *OpCode_05[] = {
  Instructions + 21,
  Instructions + 22,
  0
};

static struct x86OpCode *OpCode_06[] = {
  Instructions + 591,
  0
};

static struct x86OpCode *OpCode_07[] = {
  Instructions + 537,
  0
};

static struct x86OpCode *OpCode_08[] = {
  Instructions + 485,
  0
};

static struct x86OpCode *OpCode_09[] = {
  Instructions + 486,
  Instructions + 487,
  0
};

static struct x86OpCode *OpCode_0A[] = {
  Instructions + 488,
  0
};

static struct x86OpCode *OpCode_0B[] = {
  Instructions + 489,
  Instructions + 490,
  0
};

static struct x86OpCode *OpCode_0C[] = {
  Instructions + 477,
  0
};

static struct x86OpCode *OpCode_0D[] = {
  Instructions + 478,
  Instructions + 479,
  0
};

static struct x86OpCode *OpCode_0E[] = {
  Instructions + 588,
  0
};

static struct x86OpCode *OpCode_0F[] = {
  Instructions + 34,
  Instructions + 52,
  Instructions + 53,
  Instructions + 54,
  Instructions + 55,
  Instructions + 56,
  Instructions + 57,
  Instructions + 58,
  Instructions + 59,
  Instructions + 60,
  Instructions + 61,
  Instructions + 62,
  Instructions + 63,
  Instructions + 64,
  Instructions + 65,
  Instructions + 66,
  Instructions + 67,
  Instructions + 68,
  Instructions + 69,
  Instructions + 70,
  Instructions + 71,
  Instructions + 72,
  Instructions + 86,
  Instructions + 88,
  Instructions + 89,
  Instructions + 90,
  Instructions + 91,
  Instructions + 92,
  Instructions + 93,
  Instructions + 94,
  Instructions + 95,
  Instructions + 96,
  Instructions + 97,
  Instructions + 98,
  Instructions + 99,
  Instructions + 100,
  Instructions + 101,
  Instructions + 102,
  Instructions + 103,
  Instructions + 104,
  Instructions + 105,
  Instructions + 106,
  Instructions + 107,
  Instructions + 108,
  Instructions + 109,
  Instructions + 110,
  Instructions + 111,
  Instructions + 112,
  Instructions + 113,
  Instructions + 114,
  Instructions + 115,
  Instructions + 116,
  Instructions + 117,
  Instructions + 118,
  Instructions + 119,
  Instructions + 137,
  Instructions + 138,
  Instructions + 139,
  Instructions + 140,
  Instructions + 141,
  Instructions + 154,
  Instructions + 299,
  Instructions + 300,
  Instructions + 322,
  Instructions + 323,
  Instructions + 327,
  Instructions + 328,
  Instructions + 330,
  Instructions + 331,
  Instructions + 334,
  Instructions + 335,
  Instructions + 337,
  Instructions + 338,
  Instructions + 340,
  Instructions + 341,
  Instructions + 343,
  Instructions + 344,
  Instructions + 355,
  Instructions + 356,
  Instructions + 358,
  Instructions + 359,
  Instructions + 361,
  Instructions + 362,
  Instructions + 364,
  Instructions + 365,
  Instructions + 367,
  Instructions + 368,
  Instructions + 370,
  Instructions + 371,
  Instructions + 373,
  Instructions + 374,
  Instructions + 376,
  Instructions + 377,
  Instructions + 379,
  Instructions + 380,
  Instructions + 382,
  Instructions + 383,
  Instructions + 385,
  Instructions + 386,
  Instructions + 395,
  Instructions + 396,
  Instructions + 397,
  Instructions + 398,
  Instructions + 399,
  Instructions + 400,
  Instructions + 401,
  Instructions + 402,
  Instructions + 410,
  Instructions + 411,
  Instructions + 412,
  Instructions + 413,
  Instructions + 414,
  Instructions + 435,
  Instructions + 436,
  Instructions + 437,
  Instructions + 438,
  Instructions + 439,
  Instructions + 440,
  Instructions + 441,
  Instructions + 442,
  Instructions + 443,
  Instructions + 444,
  Instructions + 445,
  Instructions + 446,
  Instructions + 447,
  Instructions + 448,
  Instructions + 449,
  Instructions + 450,
  Instructions + 451,
  Instructions + 457,
  Instructions + 458,
  Instructions + 459,
  Instructions + 460,
  Instructions + 461,
  Instructions + 462,
  Instructions + 463,
  Instructions + 464,
  Instructions + 468,
  Instructions + 491,
  Instructions + 501,
  Instructions + 502,
  Instructions + 503,
  Instructions + 504,
  Instructions + 505,
  Instructions + 506,
  Instructions + 507,
  Instructions + 508,
  Instructions + 509,
  Instructions + 510,
  Instructions + 511,
  Instructions + 512,
  Instructions + 513,
  Instructions + 514,
  Instructions + 515,
  Instructions + 516,
  Instructions + 517,
  Instructions + 518,
  Instructions + 519,
  Instructions + 520,
  Instructions + 521,
  Instructions + 522,
  Instructions + 523,
  Instructions + 524,
  Instructions + 525,
  Instructions + 526,
  Instructions + 527,
  Instructions + 528,
  Instructions + 529,
  Instructions + 530,
  Instructions + 531,
  Instructions + 539,
  Instructions + 540,
  Instructions + 545,
  Instructions + 546,
  Instructions + 547,
  Instructions + 548,
  Instructions + 549,
  Instructions + 550,
  Instructions + 551,
  Instructions + 552,
  Instructions + 553,
  Instructions + 554,
  Instructions + 555,
  Instructions + 556,
  Instructions + 557,
  Instructions + 558,
  Instructions + 559,
  Instructions + 560,
  Instructions + 561,
  Instructions + 562,
  Instructions + 563,
  Instructions + 564,
  Instructions + 565,
  Instructions + 566,
  Instructions + 567,
  Instructions + 568,
  Instructions + 569,
  Instructions + 570,
  Instructions + 571,
  Instructions + 572,
  Instructions + 573,
  Instructions + 574,
  Instructions + 575,
  Instructions + 576,
  Instructions + 577,
  Instructions + 578,
  Instructions + 579,
  Instructions + 580,
  Instructions + 592,
  Instructions + 593,
  Instructions + 598,
  Instructions + 608,
  Instructions + 619,
  Instructions + 620,
  Instructions + 621,
  Instructions + 644,
  Instructions + 645,
  Instructions + 674,
  Instructions + 675,
  Instructions + 676,
  Instructions + 677,
  Instructions + 678,
  Instructions + 679,
  Instructions + 680,
  Instructions + 681,
  Instructions + 682,
  Instructions + 683,
  Instructions + 684,
  Instructions + 685,
  Instructions + 686,
  Instructions + 687,
  Instructions + 688,
  Instructions + 689,
  Instructions + 690,
  Instructions + 691,
  Instructions + 701,
  Instructions + 702,
  Instructions + 703,
  Instructions + 704,
  Instructions + 714,
  Instructions + 715,
  Instructions + 716,
  Instructions + 717,
  Instructions + 718,
  Instructions + 719,
  Instructions + 720,
  Instructions + 721,
  Instructions + 722,
  Instructions + 723,
  Instructions + 724,
  Instructions + 729,
  Instructions + 733,
  Instructions + 748,
  Instructions + 750,
  Instructions + 751,
  Instructions + 761,
  Instructions + 762,
  Instructions + 763,
  Instructions + 764,
  Instructions + 765,
  Instructions + 766,
  Instructions + 768,
  Instructions + 769,
  Instructions + 770,
  Instructions + 771,
  Instructions + 772,
  Instructions + 793,
  0
};

static struct x86OpCode *OpCode_10[] = {
  Instructions + 14,
  0
};

static struct x86OpCode *OpCode_11[] = {
  Instructions + 15,
  Instructions + 16,
  0
};

static struct x86OpCode *OpCode_12[] = {
  Instructions + 17,
  0
};

static struct x86OpCode *OpCode_13[] = {
  Instructions + 18,
  Instructions + 19,
  0
};

static struct x86OpCode *OpCode_14[] = {
  Instructions + 6,
  0
};

static struct x86OpCode *OpCode_15[] = {
  Instructions + 7,
  Instructions + 8,
  0
};

static struct x86OpCode *OpCode_16[] = {
  Instructions + 589,
  0
};

static struct x86OpCode *OpCode_17[] = {
  Instructions + 538,
  0
};

static struct x86OpCode *OpCode_18[] = {
  Instructions + 665,
  0
};

static struct x86OpCode *OpCode_19[] = {
  Instructions + 666,
  Instructions + 667,
  0
};

static struct x86OpCode *OpCode_1A[] = {
  Instructions + 668,
  0
};

static struct x86OpCode *OpCode_1B[] = {
  Instructions + 669,
  Instructions + 670,
  0
};

static struct x86OpCode *OpCode_1C[] = {
  Instructions + 657,
  0
};

static struct x86OpCode *OpCode_1D[] = {
  Instructions + 658,
  Instructions + 659,
  0
};

static struct x86OpCode *OpCode_1E[] = {
  Instructions + 590,
  0
};

static struct x86OpCode *OpCode_1F[] = {
  Instructions + 536,
  0
};

static struct x86OpCode *OpCode_20[] = {
  Instructions + 43,
  0
};

static struct x86OpCode *OpCode_21[] = {
  Instructions + 44,
  Instructions + 45,
  0
};

static struct x86OpCode *OpCode_22[] = {
  Instructions + 46,
  0
};

static struct x86OpCode *OpCode_23[] = {
  Instructions + 47,
  Instructions + 48,
  0
};

static struct x86OpCode *OpCode_24[] = {
  Instructions + 35,
  0
};

static struct x86OpCode *OpCode_25[] = {
  Instructions + 36,
  Instructions + 37,
  0
};

static struct x86OpCode *OpCode_26[] = {
  0
};

static struct x86OpCode *OpCode_27[] = {
  Instructions + 144,
  0
};

static struct x86OpCode *OpCode_28[] = {
  Instructions + 742,
  0
};

static struct x86OpCode *OpCode_29[] = {
  Instructions + 743,
  Instructions + 744,
  0
};

static struct x86OpCode *OpCode_2A[] = {
  Instructions + 745,
  0
};

static struct x86OpCode *OpCode_2B[] = {
  Instructions + 746,
  Instructions + 747,
  0
};

static struct x86OpCode *OpCode_2C[] = {
  Instructions + 734,
  0
};

static struct x86OpCode *OpCode_2D[] = {
  Instructions + 735,
  Instructions + 736,
  0
};

static struct x86OpCode *OpCode_2E[] = {
  0
};

static struct x86OpCode *OpCode_2F[] = {
  Instructions + 145,
  0
};

static struct x86OpCode *OpCode_30[] = {
  Instructions + 787,
  0
};

static struct x86OpCode *OpCode_31[] = {
  Instructions + 788,
  Instructions + 789,
  0
};

static struct x86OpCode *OpCode_32[] = {
  Instructions + 790,
  0
};

static struct x86OpCode *OpCode_33[] = {
  Instructions + 791,
  Instructions + 792,
  0
};

static struct x86OpCode *OpCode_34[] = {
  Instructions + 779,
  0
};

static struct x86OpCode *OpCode_35[] = {
  Instructions + 780,
  Instructions + 781,
  0
};

static struct x86OpCode *OpCode_36[] = {
  0
};

static struct x86OpCode *OpCode_37[] = {
  Instructions + 0,
  0
};

static struct x86OpCode *OpCode_38[] = {
  Instructions + 128,
  0
};

static struct x86OpCode *OpCode_39[] = {
  Instructions + 129,
  Instructions + 130,
  0
};

static struct x86OpCode *OpCode_3A[] = {
  Instructions + 131,
  0
};

static struct x86OpCode *OpCode_3B[] = {
  Instructions + 132,
  Instructions + 133,
  0
};

static struct x86OpCode *OpCode_3C[] = {
  Instructions + 120,
  0
};

static struct x86OpCode *OpCode_3D[] = {
  Instructions + 121,
  Instructions + 122,
  0
};

static struct x86OpCode *OpCode_3E[] = {
  0
};

static struct x86OpCode *OpCode_3F[] = {
  Instructions + 5,
  0
};

static struct x86OpCode *OpCode_40[] = {
  Instructions + 314,
  Instructions + 315,
  0
};

static struct x86OpCode *OpCode_41[] = {
  0
};

static struct x86OpCode *OpCode_42[] = {
  0
};

static struct x86OpCode *OpCode_43[] = {
  0
};

static struct x86OpCode *OpCode_44[] = {
  0
};

static struct x86OpCode *OpCode_45[] = {
  0
};

static struct x86OpCode *OpCode_46[] = {
  0
};

static struct x86OpCode *OpCode_47[] = {
  0
};

static struct x86OpCode *OpCode_48[] = {
  Instructions + 149,
  Instructions + 150,
  0
};

static struct x86OpCode *OpCode_49[] = {
  0
};

static struct x86OpCode *OpCode_4A[] = {
  0
};

static struct x86OpCode *OpCode_4B[] = {
  0
};

static struct x86OpCode *OpCode_4C[] = {
  0
};

static struct x86OpCode *OpCode_4D[] = {
  0
};

static struct x86OpCode *OpCode_4E[] = {
  0
};

static struct x86OpCode *OpCode_4F[] = {
  0
};

static struct x86OpCode *OpCode_50[] = {
  Instructions + 583,
  Instructions + 584,
  0
};

static struct x86OpCode *OpCode_51[] = {
  0
};

static struct x86OpCode *OpCode_52[] = {
  0
};

static struct x86OpCode *OpCode_53[] = {
  0
};

static struct x86OpCode *OpCode_54[] = {
  0
};

static struct x86OpCode *OpCode_55[] = {
  0
};

static struct x86OpCode *OpCode_56[] = {
  0
};

static struct x86OpCode *OpCode_57[] = {
  0
};

static struct x86OpCode *OpCode_58[] = {
  Instructions + 534,
  Instructions + 535,
  0
};

static struct x86OpCode *OpCode_59[] = {
  0
};

static struct x86OpCode *OpCode_5A[] = {
  0
};

static struct x86OpCode *OpCode_5B[] = {
  0
};

static struct x86OpCode *OpCode_5C[] = {
  0
};

static struct x86OpCode *OpCode_5D[] = {
  0
};

static struct x86OpCode *OpCode_5E[] = {
  0
};

static struct x86OpCode *OpCode_5F[] = {
  0
};

static struct x86OpCode *OpCode_60[] = {
  Instructions + 594,
  Instructions + 595,
  0
};

static struct x86OpCode *OpCode_61[] = {
  Instructions + 541,
  Instructions + 542,
  0
};

static struct x86OpCode *OpCode_62[] = {
  Instructions + 50,
  Instructions + 51,
  0
};

static struct x86OpCode *OpCode_63[] = {
  Instructions + 49,
  0
};

static struct x86OpCode *OpCode_64[] = {
  0
};

static struct x86OpCode *OpCode_65[] = {
  0
};

static struct x86OpCode *OpCode_66[] = {
  0
};

static struct x86OpCode *OpCode_67[] = {
  0
};

static struct x86OpCode *OpCode_68[] = {
  Instructions + 586,
  Instructions + 587,
  0
};

static struct x86OpCode *OpCode_69[] = {
  Instructions + 303,
  Instructions + 304,
  0
};

static struct x86OpCode *OpCode_6A[] = {
  Instructions + 585,
  0
};

static struct x86OpCode *OpCode_6B[] = {
  Instructions + 301,
  Instructions + 302,
  0
};

static struct x86OpCode *OpCode_6C[] = {
  Instructions + 316,
  0
};

static struct x86OpCode *OpCode_6D[] = {
  Instructions + 317,
  Instructions + 318,
  0
};

static struct x86OpCode *OpCode_6E[] = {
  Instructions + 498,
  0
};

static struct x86OpCode *OpCode_6F[] = {
  Instructions + 499,
  Instructions + 500,
  0
};

static struct x86OpCode *OpCode_70[] = {
  Instructions + 375,
  0
};

static struct x86OpCode *OpCode_71[] = {
  Instructions + 366,
  0
};

static struct x86OpCode *OpCode_72[] = {
  Instructions + 329,
  0
};

static struct x86OpCode *OpCode_73[] = {
  Instructions + 357,
  0
};

static struct x86OpCode *OpCode_74[] = {
  Instructions + 333,
  0
};

static struct x86OpCode *OpCode_75[] = {
  Instructions + 360,
  0
};

static struct x86OpCode *OpCode_76[] = {
  Instructions + 354,
  0
};

static struct x86OpCode *OpCode_77[] = {
  Instructions + 326,
  0
};

static struct x86OpCode *OpCode_78[] = {
  Instructions + 381,
  0
};

static struct x86OpCode *OpCode_79[] = {
  Instructions + 372,
  0
};

static struct x86OpCode *OpCode_7A[] = {
  Instructions + 378,
  0
};

static struct x86OpCode *OpCode_7B[] = {
  Instructions + 369,
  0
};

static struct x86OpCode *OpCode_7C[] = {
  Instructions + 339,
  0
};

static struct x86OpCode *OpCode_7D[] = {
  Instructions + 363,
  0
};

static struct x86OpCode *OpCode_7E[] = {
  Instructions + 342,
  0
};

static struct x86OpCode *OpCode_7F[] = {
  Instructions + 336,
  0
};

static struct x86OpCode *OpCode_80[] = {
  Instructions + 9,
  Instructions + 23,
  Instructions + 38,
  Instructions + 123,
  Instructions + 480,
  Instructions + 660,
  Instructions + 737,
  Instructions + 782,
  0
};

static struct x86OpCode *OpCode_81[] = {
  Instructions + 10,
  Instructions + 11,
  Instructions + 24,
  Instructions + 25,
  Instructions + 39,
  Instructions + 40,
  Instructions + 124,
  Instructions + 125,
  Instructions + 481,
  Instructions + 482,
  Instructions + 661,
  Instructions + 662,
  Instructions + 738,
  Instructions + 739,
  Instructions + 783,
  Instructions + 784,
  0
};

static struct x86OpCode *OpCode_82[] = {
  0
};

static struct x86OpCode *OpCode_83[] = {
  Instructions + 12,
  Instructions + 13,
  Instructions + 26,
  Instructions + 27,
  Instructions + 41,
  Instructions + 42,
  Instructions + 126,
  Instructions + 127,
  Instructions + 483,
  Instructions + 484,
  Instructions + 663,
  Instructions + 664,
  Instructions + 740,
  Instructions + 741,
  Instructions + 785,
  Instructions + 786,
  0
};

static struct x86OpCode *OpCode_84[] = {
  Instructions + 758,
  0
};

static struct x86OpCode *OpCode_85[] = {
  Instructions + 759,
  Instructions + 760,
  0
};

static struct x86OpCode *OpCode_86[] = {
  Instructions + 775,
  0
};

static struct x86OpCode *OpCode_87[] = {
  Instructions + 776,
  Instructions + 777,
  0
};

static struct x86OpCode *OpCode_88[] = {
  Instructions + 415,
  0
};

static struct x86OpCode *OpCode_89[] = {
  Instructions + 416,
  Instructions + 417,
  0
};

static struct x86OpCode *OpCode_8A[] = {
  Instructions + 418,
  0
};

static struct x86OpCode *OpCode_8B[] = {
  Instructions + 419,
  Instructions + 420,
  0
};

static struct x86OpCode *OpCode_8C[] = {
  Instructions + 421,
  0
};

static struct x86OpCode *OpCode_8D[] = {
  Instructions + 389,
  Instructions + 390,
  0
};

static struct x86OpCode *OpCode_8E[] = {
  Instructions + 422,
  0
};

static struct x86OpCode *OpCode_8F[] = {
  Instructions + 532,
  Instructions + 533,
  0
};

static struct x86OpCode *OpCode_90[] = {
  Instructions + 473,
  Instructions + 773,
  Instructions + 774,
  0
};

static struct x86OpCode *OpCode_91[] = {
  0
};

static struct x86OpCode *OpCode_92[] = {
  0
};

static struct x86OpCode *OpCode_93[] = {
  0
};

static struct x86OpCode *OpCode_94[] = {
  0
};

static struct x86OpCode *OpCode_95[] = {
  0
};

static struct x86OpCode *OpCode_96[] = {
  0
};

static struct x86OpCode *OpCode_97[] = {
  0
};

static struct x86OpCode *OpCode_98[] = {
  Instructions + 81,
  Instructions + 143,
  0
};

static struct x86OpCode *OpCode_99[] = {
  Instructions + 82,
  Instructions + 142,
  0
};

static struct x86OpCode *OpCode_9A[] = {
  Instructions + 77,
  Instructions + 78,
  0
};

static struct x86OpCode *OpCode_9B[] = {
  Instructions + 166,
  Instructions + 213,
  Instructions + 255,
  Instructions + 263,
  Instructions + 264,
  Instructions + 269,
  Instructions + 270,
  Instructions + 767,
  0
};

static struct x86OpCode *OpCode_9C[] = {
  Instructions + 596,
  Instructions + 597,
  0
};

static struct x86OpCode *OpCode_9D[] = {
  Instructions + 543,
  Instructions + 544,
  0
};

static struct x86OpCode *OpCode_9E[] = {
  Instructions + 647,
  0
};

static struct x86OpCode *OpCode_9F[] = {
  Instructions + 384,
  0
};

static struct x86OpCode *OpCode_A0[] = {
  Instructions + 423,
  0
};

static struct x86OpCode *OpCode_A1[] = {
  Instructions + 424,
  Instructions + 425,
  0
};

static struct x86OpCode *OpCode_A2[] = {
  Instructions + 426,
  0
};

static struct x86OpCode *OpCode_A3[] = {
  Instructions + 427,
  Instructions + 428,
  0
};

static struct x86OpCode *OpCode_A4[] = {
  Instructions + 452,
  0
};

static struct x86OpCode *OpCode_A5[] = {
  Instructions + 453,
  Instructions + 456,
  0
};

static struct x86OpCode *OpCode_A6[] = {
  Instructions + 134,
  0
};

static struct x86OpCode *OpCode_A7[] = {
  Instructions + 135,
  Instructions + 136,
  0
};

static struct x86OpCode *OpCode_A8[] = {
  Instructions + 752,
  0
};

static struct x86OpCode *OpCode_A9[] = {
  Instructions + 753,
  Instructions + 754,
  0
};

static struct x86OpCode *OpCode_AA[] = {
  Instructions + 730,
  0
};

static struct x86OpCode *OpCode_AB[] = {
  Instructions + 731,
  Instructions + 732,
  0
};

static struct x86OpCode *OpCode_AC[] = {
  Instructions + 404,
  0
};

static struct x86OpCode *OpCode_AD[] = {
  Instructions + 405,
  Instructions + 406,
  0
};

static struct x86OpCode *OpCode_AE[] = {
  Instructions + 671,
  0
};

static struct x86OpCode *OpCode_AF[] = {
  Instructions + 672,
  Instructions + 673,
  0
};

static struct x86OpCode *OpCode_B0[] = {
  Instructions + 429,
  0
};

static struct x86OpCode *OpCode_B1[] = {
  0
};

static struct x86OpCode *OpCode_B2[] = {
  0
};

static struct x86OpCode *OpCode_B3[] = {
  0
};

static struct x86OpCode *OpCode_B4[] = {
  0
};

static struct x86OpCode *OpCode_B5[] = {
  0
};

static struct x86OpCode *OpCode_B6[] = {
  0
};

static struct x86OpCode *OpCode_B7[] = {
  0
};

static struct x86OpCode *OpCode_B8[] = {
  Instructions + 430,
  Instructions + 431,
  0
};

static struct x86OpCode *OpCode_B9[] = {
  0
};

static struct x86OpCode *OpCode_BA[] = {
  0
};

static struct x86OpCode *OpCode_BB[] = {
  0
};

static struct x86OpCode *OpCode_BC[] = {
  0
};

static struct x86OpCode *OpCode_BD[] = {
  0
};

static struct x86OpCode *OpCode_BE[] = {
  0
};

static struct x86OpCode *OpCode_BF[] = {
  0
};

static struct x86OpCode *OpCode_C0[] = {
  Instructions + 601,
  Instructions + 612,
  Instructions + 628,
  Instructions + 637,
  Instructions + 650,
  Instructions + 694,
  Instructions + 707,
  0
};

static struct x86OpCode *OpCode_C1[] = {
  Instructions + 604,
  Instructions + 607,
  Instructions + 615,
  Instructions + 618,
  Instructions + 631,
  Instructions + 634,
  Instructions + 640,
  Instructions + 643,
  Instructions + 653,
  Instructions + 656,
  Instructions + 697,
  Instructions + 700,
  Instructions + 710,
  Instructions + 713,
  0
};

static struct x86OpCode *OpCode_C2[] = {
  Instructions + 625,
  0
};

static struct x86OpCode *OpCode_C3[] = {
  Instructions + 624,
  0
};

static struct x86OpCode *OpCode_C4[] = {
  Instructions + 393,
  Instructions + 394,
  0
};

static struct x86OpCode *OpCode_C5[] = {
  Instructions + 387,
  Instructions + 388,
  0
};

static struct x86OpCode *OpCode_C6[] = {
  Instructions + 432,
  0
};

static struct x86OpCode *OpCode_C7[] = {
  Instructions + 433,
  Instructions + 434,
  0
};

static struct x86OpCode *OpCode_C8[] = {
  Instructions + 155,
  0
};

static struct x86OpCode *OpCode_C9[] = {
  Instructions + 391,
  Instructions + 392,
  0
};

static struct x86OpCode *OpCode_CA[] = {
  Instructions + 623,
  0
};

static struct x86OpCode *OpCode_CB[] = {
  Instructions + 622,
  0
};

static struct x86OpCode *OpCode_CC[] = {
  Instructions + 320,
  0
};

static struct x86OpCode *OpCode_CD[] = {
  Instructions + 319,
  0
};

static struct x86OpCode *OpCode_CE[] = {
  Instructions + 321,
  0
};

static struct x86OpCode *OpCode_CF[] = {
  Instructions + 324,
  Instructions + 325,
  0
};

static struct x86OpCode *OpCode_D0[] = {
  Instructions + 599,
  Instructions + 610,
  Instructions + 626,
  Instructions + 635,
  Instructions + 648,
  Instructions + 692,
  Instructions + 705,
  0
};

static struct x86OpCode *OpCode_D1[] = {
  Instructions + 602,
  Instructions + 605,
  Instructions + 613,
  Instructions + 616,
  Instructions + 629,
  Instructions + 632,
  Instructions + 638,
  Instructions + 641,
  Instructions + 651,
  Instructions + 654,
  Instructions + 695,
  Instructions + 698,
  Instructions + 708,
  Instructions + 711,
  0
};

static struct x86OpCode *OpCode_D2[] = {
  Instructions + 600,
  Instructions + 611,
  Instructions + 627,
  Instructions + 636,
  Instructions + 649,
  Instructions + 693,
  Instructions + 706,
  0
};

static struct x86OpCode *OpCode_D3[] = {
  Instructions + 603,
  Instructions + 606,
  Instructions + 614,
  Instructions + 617,
  Instructions + 630,
  Instructions + 633,
  Instructions + 639,
  Instructions + 642,
  Instructions + 652,
  Instructions + 655,
  Instructions + 696,
  Instructions + 699,
  Instructions + 709,
  Instructions + 712,
  0
};

static struct x86OpCode *OpCode_D4[] = {
  Instructions + 3,
  Instructions + 4,
  0
};

static struct x86OpCode *OpCode_D5[] = {
  Instructions + 1,
  Instructions + 2,
  0
};

static struct x86OpCode *OpCode_D6[] = {
  0
};

static struct x86OpCode *OpCode_D7[] = {
  Instructions + 778,
  0
};

static struct x86OpCode *OpCode_D8[] = {
  Instructions + 158,
  Instructions + 160,
  Instructions + 175,
  Instructions + 177,
  Instructions + 180,
  Instructions + 182,
  Instructions + 186,
  Instructions + 188,
  Instructions + 191,
  Instructions + 193,
  Instructions + 236,
  Instructions + 238,
  Instructions + 271,
  Instructions + 273,
  Instructions + 276,
  Instructions + 278,
  0
};

static struct x86OpCode *OpCode_D9[] = {
  Instructions + 156,
  Instructions + 157,
  Instructions + 165,
  Instructions + 184,
  Instructions + 185,
  Instructions + 212,
  Instructions + 223,
  Instructions + 226,
  Instructions + 227,
  Instructions + 228,
  Instructions + 229,
  Instructions + 230,
  Instructions + 231,
  Instructions + 232,
  Instructions + 233,
  Instructions + 234,
  Instructions + 235,
  Instructions + 243,
  Instructions + 245,
  Instructions + 246,
  Instructions + 249,
  Instructions + 250,
  Instructions + 251,
  Instructions + 252,
  Instructions + 253,
  Instructions + 256,
  Instructions + 257,
  Instructions + 258,
  Instructions + 259,
  Instructions + 260,
  Instructions + 265,
  Instructions + 281,
  Instructions + 287,
  Instructions + 288,
  Instructions + 289,
  Instructions + 290,
  Instructions + 291,
  0
};

static struct x86OpCode *OpCode_DA[] = {
  Instructions + 167,
  Instructions + 168,
  Instructions + 169,
  Instructions + 174,
  Instructions + 197,
  Instructions + 200,
  Instructions + 202,
  Instructions + 203,
  Instructions + 205,
  Instructions + 210,
  Instructions + 219,
  Instructions + 221,
  Instructions + 286,
  0
};

static struct x86OpCode *OpCode_DB[] = {
  Instructions + 170,
  Instructions + 171,
  Instructions + 172,
  Instructions + 173,
  Instructions + 178,
  Instructions + 208,
  Instructions + 215,
  Instructions + 217,
  Instructions + 225,
  Instructions + 241,
  Instructions + 242,
  Instructions + 267,
  Instructions + 283,
  0
};

static struct x86OpCode *OpCode_DC[] = {
  Instructions + 159,
  Instructions + 161,
  Instructions + 176,
  Instructions + 181,
  Instructions + 187,
  Instructions + 189,
  Instructions + 192,
  Instructions + 194,
  Instructions + 237,
  Instructions + 239,
  Instructions + 272,
  Instructions + 274,
  Instructions + 277,
  Instructions + 279,
  0
};

static struct x86OpCode *OpCode_DD[] = {
  Instructions + 196,
  Instructions + 224,
  Instructions + 244,
  Instructions + 247,
  Instructions + 254,
  Instructions + 261,
  Instructions + 262,
  Instructions + 266,
  Instructions + 268,
  Instructions + 282,
  Instructions + 285,
  0
};

static struct x86OpCode *OpCode_DE[] = {
  Instructions + 162,
  Instructions + 183,
  Instructions + 190,
  Instructions + 195,
  Instructions + 198,
  Instructions + 199,
  Instructions + 201,
  Instructions + 204,
  Instructions + 206,
  Instructions + 211,
  Instructions + 220,
  Instructions + 222,
  Instructions + 240,
  Instructions + 275,
  Instructions + 280,
  0
};

static struct x86OpCode *OpCode_DF[] = {
  Instructions + 163,
  Instructions + 164,
  Instructions + 179,
  Instructions + 207,
  Instructions + 209,
  Instructions + 214,
  Instructions + 216,
  Instructions + 218,
  Instructions + 248,
  Instructions + 284,
  0
};

static struct x86OpCode *OpCode_E0[] = {
  Instructions + 409,
  0
};

static struct x86OpCode *OpCode_E1[] = {
  Instructions + 408,
  0
};

static struct x86OpCode *OpCode_E2[] = {
  Instructions + 407,
  0
};

static struct x86OpCode *OpCode_E3[] = {
  Instructions + 332,
  0
};

static struct x86OpCode *OpCode_E4[] = {
  Instructions + 305,
  0
};

static struct x86OpCode *OpCode_E5[] = {
  Instructions + 306,
  Instructions + 307,
  0
};

static struct x86OpCode *OpCode_E6[] = {
  Instructions + 492,
  0
};

static struct x86OpCode *OpCode_E7[] = {
  Instructions + 493,
  Instructions + 494,
  0
};

static struct x86OpCode *OpCode_E8[] = {
  Instructions + 73,
  Instructions + 74,
  0
};

static struct x86OpCode *OpCode_E9[] = {
  Instructions + 346,
  Instructions + 347,
  0
};

static struct x86OpCode *OpCode_EA[] = {
  Instructions + 350,
  Instructions + 351,
  0
};

static struct x86OpCode *OpCode_EB[] = {
  Instructions + 345,
  0
};

static struct x86OpCode *OpCode_EC[] = {
  Instructions + 308,
  0
};

static struct x86OpCode *OpCode_ED[] = {
  Instructions + 309,
  Instructions + 310,
  0
};

static struct x86OpCode *OpCode_EE[] = {
  Instructions + 495,
  0
};

static struct x86OpCode *OpCode_EF[] = {
  Instructions + 496,
  Instructions + 497,
  0
};

static struct x86OpCode *OpCode_F0[] = {
  Instructions + 403,
  0
};

static struct x86OpCode *OpCode_F1[] = {
  0
};

static struct x86OpCode *OpCode_F2[] = {
  0
};

static struct x86OpCode *OpCode_F3[] = {
  Instructions + 454,
  Instructions + 455,
  Instructions + 469,
  Instructions + 609,
  Instructions + 646,
  Instructions + 725,
  Instructions + 749,
  0
};

static struct x86OpCode *OpCode_F4[] = {
  Instructions + 292,
  0
};

static struct x86OpCode *OpCode_F5[] = {
  Instructions + 87,
  0
};

static struct x86OpCode *OpCode_F6[] = {
  Instructions + 151,
  Instructions + 293,
  Instructions + 296,
  Instructions + 465,
  Instructions + 470,
  Instructions + 474,
  Instructions + 755,
  0
};

static struct x86OpCode *OpCode_F7[] = {
  Instructions + 152,
  Instructions + 153,
  Instructions + 294,
  Instructions + 295,
  Instructions + 297,
  Instructions + 298,
  Instructions + 466,
  Instructions + 467,
  Instructions + 471,
  Instructions + 472,
  Instructions + 475,
  Instructions + 476,
  Instructions + 756,
  Instructions + 757,
  0
};

static struct x86OpCode *OpCode_F8[] = {
  Instructions + 83,
  0
};

static struct x86OpCode *OpCode_F9[] = {
  Instructions + 726,
  0
};

static struct x86OpCode *OpCode_FA[] = {
  Instructions + 85,
  0
};

static struct x86OpCode *OpCode_FB[] = {
  Instructions + 728,
  0
};

static struct x86OpCode *OpCode_FC[] = {
  Instructions + 84,
  0
};

static struct x86OpCode *OpCode_FD[] = {
  Instructions + 727,
  0
};

static struct x86OpCode *OpCode_FE[] = {
  Instructions + 146,
  Instructions + 311,
  0
};

static struct x86OpCode *OpCode_FF[] = {
  Instructions + 75,
  Instructions + 76,
  Instructions + 79,
  Instructions + 80,
  Instructions + 147,
  Instructions + 148,
  Instructions + 312,
  Instructions + 313,
  Instructions + 348,
  Instructions + 349,
  Instructions + 352,
  Instructions + 353,
  Instructions + 581,
  Instructions + 582,
  0
};

struct x86OpCode **x86OpCodes[] = {
  OpCode_00,
  OpCode_01,
  OpCode_02,
  OpCode_03,
  OpCode_04,
  OpCode_05,
  OpCode_06,
  OpCode_07,
  OpCode_08,
  OpCode_09,
  OpCode_0A,
  OpCode_0B,
  OpCode_0C,
  OpCode_0D,
  OpCode_0E,
  OpCode_0F,
  OpCode_10,
  OpCode_11,
  OpCode_12,
  OpCode_13,
  OpCode_14,
  OpCode_15,
  OpCode_16,
  OpCode_17,
  OpCode_18,
  OpCode_19,
  OpCode_1A,
  OpCode_1B,
  OpCode_1C,
  OpCode_1D,
  OpCode_1E,
  OpCode_1F,
  OpCode_20,
  OpCode_21,
  OpCode_22,
  OpCode_23,
  OpCode_24,
  OpCode_25,
  OpCode_26,
  OpCode_27,
  OpCode_28,
  OpCode_29,
  OpCode_2A,
  OpCode_2B,
  OpCode_2C,
  OpCode_2D,
  OpCode_2E,
  OpCode_2F,
  OpCode_30,
  OpCode_31,
  OpCode_32,
  OpCode_33,
  OpCode_34,
  OpCode_35,
  OpCode_36,
  OpCode_37,
  OpCode_38,
  OpCode_39,
  OpCode_3A,
  OpCode_3B,
  OpCode_3C,
  OpCode_3D,
  OpCode_3E,
  OpCode_3F,
  OpCode_40,
  OpCode_41,
  OpCode_42,
  OpCode_43,
  OpCode_44,
  OpCode_45,
  OpCode_46,
  OpCode_47,
  OpCode_48,
  OpCode_49,
  OpCode_4A,
  OpCode_4B,
  OpCode_4C,
  OpCode_4D,
  OpCode_4E,
  OpCode_4F,
  OpCode_50,
  OpCode_51,
  OpCode_52,
  OpCode_53,
  OpCode_54,
  OpCode_55,
  OpCode_56,
  OpCode_57,
  OpCode_58,
  OpCode_59,
  OpCode_5A,
  OpCode_5B,
  OpCode_5C,
  OpCode_5D,
  OpCode_5E,
  OpCode_5F,
  OpCode_60,
  OpCode_61,
  OpCode_62,
  OpCode_63,
  OpCode_64,
  OpCode_65,
  OpCode_66,
  OpCode_67,
  OpCode_68,
  OpCode_69,
  OpCode_6A,
  OpCode_6B,
  OpCode_6C,
  OpCode_6D,
  OpCode_6E,
  OpCode_6F,
  OpCode_70,
  OpCode_71,
  OpCode_72,
  OpCode_73,
  OpCode_74,
  OpCode_75,
  OpCode_76,
  OpCode_77,
  OpCode_78,
  OpCode_79,
  OpCode_7A,
  OpCode_7B,
  OpCode_7C,
  OpCode_7D,
  OpCode_7E,
  OpCode_7F,
  OpCode_80,
  OpCode_81,
  OpCode_82,
  OpCode_83,
  OpCode_84,
  OpCode_85,
  OpCode_86,
  OpCode_87,
  OpCode_88,
  OpCode_89,
  OpCode_8A,
  OpCode_8B,
  OpCode_8C,
  OpCode_8D,
  OpCode_8E,
  OpCode_8F,
  OpCode_90,
  OpCode_91,
  OpCode_92,
  OpCode_93,
  OpCode_94,
  OpCode_95,
  OpCode_96,
  OpCode_97,
  OpCode_98,
  OpCode_99,
  OpCode_9A,
  OpCode_9B,
  OpCode_9C,
  OpCode_9D,
  OpCode_9E,
  OpCode_9F,
  OpCode_A0,
  OpCode_A1,
  OpCode_A2,
  OpCode_A3,
  OpCode_A4,
  OpCode_A5,
  OpCode_A6,
  OpCode_A7,
  OpCode_A8,
  OpCode_A9,
  OpCode_AA,
  OpCode_AB,
  OpCode_AC,
  OpCode_AD,
  OpCode_AE,
  OpCode_AF,
  OpCode_B0,
  OpCode_B1,
  OpCode_B2,
  OpCode_B3,
  OpCode_B4,
  OpCode_B5,
  OpCode_B6,
  OpCode_B7,
  OpCode_B8,
  OpCode_B9,
  OpCode_BA,
  OpCode_BB,
  OpCode_BC,
  OpCode_BD,
  OpCode_BE,
  OpCode_BF,
  OpCode_C0,
  OpCode_C1,
  OpCode_C2,
  OpCode_C3,
  OpCode_C4,
  OpCode_C5,
  OpCode_C6,
  OpCode_C7,
  OpCode_C8,
  OpCode_C9,
  OpCode_CA,
  OpCode_CB,
  OpCode_CC,
  OpCode_CD,
  OpCode_CE,
  OpCode_CF,
  OpCode_D0,
  OpCode_D1,
  OpCode_D2,
  OpCode_D3,
  OpCode_D4,
  OpCode_D5,
  OpCode_D6,
  OpCode_D7,
  OpCode_D8,
  OpCode_D9,
  OpCode_DA,
  OpCode_DB,
  OpCode_DC,
  OpCode_DD,
  OpCode_DE,
  OpCode_DF,
  OpCode_E0,
  OpCode_E1,
  OpCode_E2,
  OpCode_E3,
  OpCode_E4,
  OpCode_E5,
  OpCode_E6,
  OpCode_E7,
  OpCode_E8,
  OpCode_E9,
  OpCode_EA,
  OpCode_EB,
  OpCode_EC,
  OpCode_ED,
  OpCode_EE,
  OpCode_EF,
  OpCode_F0,
  OpCode_F1,
  OpCode_F2,
  OpCode_F3,
  OpCode_F4,
  OpCode_F5,
  OpCode_F6,
  OpCode_F7,
  OpCode_F8,
  OpCode_F9,
  OpCode_FA,
  OpCode_FB,
  OpCode_FC,
  OpCode_FD,
  OpCode_FE,
  OpCode_FF,
};
